uboot-phytec

// SPDX-License-Identifier: GPL-2.0+

/*

 * (C) Copyright 2000-2011

 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.

 */

​

#include <common.h>

#include <ata.h>

#include <dm.h>

#include <ide.h>

#include <watchdog.h>

#include <asm/io.h>

​

#ifdef __PPC__

# define EIEIO      __asm__ volatile ("eieio")

# define SYNC       __asm__ volatile ("sync")

#else

# define EIEIO      /* nothing */

# define SYNC       /* nothing */

#endif

​

/* Current offset for IDE0 / IDE1 bus access    */

ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS] = {

#if defined(CONFIG_SYS_ATA_IDE0_OFFSET)

    CONFIG_SYS_ATA_IDE0_OFFSET,

#endif

#if defined(CONFIG_SYS_ATA_IDE1_OFFSET) && (CONFIG_SYS_IDE_MAXBUS > 1)

    CONFIG_SYS_ATA_IDE1_OFFSET,

#endif

};

​

static int ide_bus_ok[CONFIG_SYS_IDE_MAXBUS];

​

struct blk_desc ide_dev_desc[CONFIG_SYS_IDE_MAXDEVICE];

​

#define IDE_TIME_OUT    2000    /* 2 sec timeout */

​

#define ATAPI_TIME_OUT  7000    /* 7 sec timeout (5 sec seems to work...) */

​

#define IDE_SPIN_UP_TIME_OUT 5000 /* 5 sec spin-up timeout */

​

#ifndef CONFIG_SYS_ATA_PORT_ADDR

#define CONFIG_SYS_ATA_PORT_ADDR(port) (port)

#endif

​

#ifdef CONFIG_IDE_RESET

extern void ide_set_reset(int idereset);

​

static void ide_reset(void)

{

    int i;

​

    for (i = 0; i < CONFIG_SYS_IDE_MAXBUS; ++i)

        ide_bus_ok[i] = 0;

    for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; ++i)

        ide_dev_desc[i].type = DEV_TYPE_UNKNOWN;

​

    ide_set_reset(1);   /* assert reset */

​

    /* the reset signal shall be asserted for et least 25 us */

    udelay(25);

​

    WATCHDOG_RESET();