uboot-phytec

// SPDX-License-Identifier: (GPL-2.0 OR MIT)

/*

 * Microsemi SoCs serial gpio driver

 *

 * Author: <lars.povlsen@microchip.com>

 *

 * Copyright (c) 2018 Microsemi Corporation

 */

​

#include <common.h>

#include <dm.h>

#include <asm/gpio.h>

#include <asm/io.h>

#include <errno.h>

#include <clk.h>

​

#define MSCC_SGPIOS_PER_BANK    32

#define MSCC_SGPIO_BANK_DEPTH   4

​

enum {

    REG_INPUT_DATA,

    REG_PORT_CONFIG,

    REG_PORT_ENABLE,

    REG_SIO_CONFIG,

    REG_SIO_CLOCK,

    MAXREG

};

​

struct mscc_sgpio_bf {

    u8 beg;

    u8 end;

};

​

struct mscc_sgpio_props {

    u8 regoff[MAXREG];

    struct mscc_sgpio_bf auto_repeat;

    struct mscc_sgpio_bf port_width;

    struct mscc_sgpio_bf clk_freq;

    struct mscc_sgpio_bf bit_source;

};

​

#define __M(bf)     GENMASK((bf).end, (bf).beg)

#define __F(bf, x)  (__M(bf) & ((x) << (bf).beg))

#define __X(bf, x)  (((x) >> (bf).beg) & GENMASK(((bf).end - (bf).beg), 0))

​

#define MSCC_M_CFG_SIO_AUTO_REPEAT(p)       BIT(p->props->auto_repeat.beg)

#define MSCC_F_CFG_SIO_PORT_WIDTH(p, x)     __F(p->props->port_width, x)

#define MSCC_M_CFG_SIO_PORT_WIDTH(p)        __M(p->props->port_width)

#define MSCC_F_CLOCK_SIO_CLK_FREQ(p, x)     __F(p->props->clk_freq, x)

#define MSCC_M_CLOCK_SIO_CLK_FREQ(p)        __M(p->props->clk_freq)

#define MSCC_F_PORT_CFG_BIT_SOURCE(p, x)    __F(p->props->bit_source, x)

#define MSCC_X_PORT_CFG_BIT_SOURCE(p, x)    __X(p->props->bit_source, x)

​

const struct mscc_sgpio_props props_luton = {

    .regoff = { 0x00, 0x09, 0x29, 0x2a, 0x2b },

    .auto_repeat = { 5, 5 },

    .port_width  = { 2, 3 },

    .clk_freq    = { 0, 11 },

    .bit_source  = { 0, 11 },

};

​

const struct mscc_sgpio_props props_ocelot = {

    .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05 },

    .auto_repeat = { 10, 10 },

    .port_width  = {  7, 8  },

    .clk_freq    = {  8, 19 },

    .bit_source  = { 12, 23 },

};

​

struct mscc_sgpio_priv {

    u32 bitcount;

    u32 ports;

    u32 clock;

    u32 mode[MSCC_SGPIOS_PER_BANK];

    u32 __iomem *regs;

    const struct mscc_sgpio_props *props;

};

​

static inline u32 sgpio_readl(struct mscc_sgpio_priv *priv, u32 rno, u32 off)

{

    u32 __iomem *reg = &priv->regs[priv->props->regoff[rno] + off];

​

    return readl(reg);

}

​

static inline void sgpio_writel(struct mscc_sgpio_priv *priv,

                u32 val, u32 rno, u32 off)

{

    u32 __iomem *reg = &priv->regs[priv->props->regoff[rno] + off];

​

    writel(val, reg);

}