uboot-phytec

// SPDX-License-Identifier: GPL-2.0+

/*

 * Copyright (c) 2016, Google Inc

 *

 * (C) Copyright 2002

 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch

 */

​

#include <common.h>

#include <dm.h>

#include <i2c.h>

#include <asm/arch/clk.h>

#include <asm/arch/cpu.h>

#include <asm/arch/pinmux.h>

#include "s3c24x0_i2c.h"

​

DECLARE_GLOBAL_DATA_PTR;

​

/* HSI2C-specific register description */

​

/* I2C_CTL Register bits */

#define HSI2C_FUNC_MODE_I2C     (1u << 0)

#define HSI2C_MASTER            (1u << 3)

#define HSI2C_RXCHON            (1u << 6)   /* Write/Send */

#define HSI2C_TXCHON            (1u << 7)   /* Read/Receive */

#define HSI2C_SW_RST            (1u << 31)

​

/* I2C_FIFO_CTL Register bits */

#define HSI2C_RXFIFO_EN         (1u << 0)

#define HSI2C_TXFIFO_EN         (1u << 1)

#define HSI2C_TXFIFO_TRIGGER_LEVEL  (0x20 << 16)

#define HSI2C_RXFIFO_TRIGGER_LEVEL  (0x20 << 4)

​

/* I2C_TRAILING_CTL Register bits */

#define HSI2C_TRAILING_COUNT        (0xff)

​

/* I2C_INT_EN Register bits */

#define HSI2C_TX_UNDERRUN_EN        (1u << 2)

#define HSI2C_TX_OVERRUN_EN     (1u << 3)

#define HSI2C_RX_UNDERRUN_EN        (1u << 4)

#define HSI2C_RX_OVERRUN_EN     (1u << 5)

#define HSI2C_INT_TRAILING_EN       (1u << 6)

#define HSI2C_INT_I2C_EN        (1u << 9)

​

#define HSI2C_INT_ERROR_MASK    (HSI2C_TX_UNDERRUN_EN |\

                 HSI2C_TX_OVERRUN_EN  |\

                 HSI2C_RX_UNDERRUN_EN |\

                 HSI2C_RX_OVERRUN_EN  |\

                 HSI2C_INT_TRAILING_EN)

​

/* I2C_CONF Register bits */

#define HSI2C_AUTO_MODE         (1u << 31)

#define HSI2C_10BIT_ADDR_MODE       (1u << 30)

#define HSI2C_HS_MODE           (1u << 29)

​

/* I2C_AUTO_CONF Register bits */

#define HSI2C_READ_WRITE        (1u << 16)

#define HSI2C_STOP_AFTER_TRANS      (1u << 17)

#define HSI2C_MASTER_RUN        (1u << 31)

​

/* I2C_TIMEOUT Register bits */

#define HSI2C_TIMEOUT_EN        (1u << 31)

​