uboot-phytec

// SPDX-License-Identifier: GPL-2.0+

/*

 * (C) Copyright 2012 SAMSUNG Electronics

 * Jaehoon Chung <jh80.chung@samsung.com>

 */

​

#include <common.h>

#include <dwmmc.h>

#include <fdtdec.h>

#include <linux/libfdt.h>

#include <malloc.h>

#include <errno.h>

#include <asm/arch/dwmmc.h>

#include <asm/arch/clk.h>

#include <asm/arch/pinmux.h>

#include <asm/arch/power.h>

#include <asm/gpio.h>

​

#define DWMMC_MAX_CH_NUM        4

#define DWMMC_MAX_FREQ          52000000

#define DWMMC_MIN_FREQ          400000

#define DWMMC_MMC0_SDR_TIMING_VAL   0x03030001

#define DWMMC_MMC2_SDR_TIMING_VAL   0x03020001

​

#ifdef CONFIG_DM_MMC

#include <dm.h>

DECLARE_GLOBAL_DATA_PTR;

​

struct exynos_mmc_plat {

    struct mmc_config cfg;

    struct mmc mmc;

};

#endif

​

/* Exynos implmentation specific drver private data */

struct dwmci_exynos_priv_data {

#ifdef CONFIG_DM_MMC

    struct dwmci_host host;

#endif

    u32 sdr_timing;

};

​

/*

 * Function used as callback function to initialise the

 * CLKSEL register for every mmc channel.

 */

static void exynos_dwmci_clksel(struct dwmci_host *host)

{

    struct dwmci_exynos_priv_data *priv = host->priv;

​

    dwmci_writel(host, DWMCI_CLKSEL, priv->sdr_timing);

}

​

unsigned int exynos_dwmci_get_clk(struct dwmci_host *host, uint freq)

{

    unsigned long sclk;

    int8_t clk_div;

​

    /*

     * Since SDCLKIN is divided inside controller by the DIVRATIO

     * value set in the CLKSEL register, we need to use the same output

     * clock value to calculate the CLKDIV value.

     * as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1)