uboot-phytec

/*

 *  This is a driver for the SDHC controller found in Freescale MX2/MX3

 *  SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).

 *  Unlike the hardware found on MX1, this hardware just works and does

 *  not need all the quirks found in imxmmc.c, hence the seperate driver.

 *

 *  Copyright (C) 2009 Ilya Yanok, <yanok@emcraft.com>

 *  Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>

 *  Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>

 *

 *  derived from pxamci.c by Russell King

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 */

​

#include <config.h>

#include <common.h>

#include <command.h>

#include <mmc.h>

#include <part.h>

#include <malloc.h>

#include <mmc.h>

#include <linux/errno.h>

#include <asm/io.h>

#include <asm/arch/clock.h>

​

#define DRIVER_NAME "mxc-mmc"

​

struct mxcmci_regs {

    u32 str_stp_clk;

    u32 status;

    u32 clk_rate;

    u32 cmd_dat_cont;

    u32 res_to;

    u32 read_to;

    u32 blk_len;

    u32 nob;

    u32 rev_no;

    u32 int_cntr;

    u32 cmd;

    u32 arg;

    u32 pad;

    u32 res_fifo;

    u32 buffer_access;

};

​

#define STR_STP_CLK_RESET               (1 << 3)

#define STR_STP_CLK_START_CLK           (1 << 1)

#define STR_STP_CLK_STOP_CLK            (1 << 0)

​

#define STATUS_CARD_INSERTION       (1 << 31)

#define STATUS_CARD_REMOVAL     (1 << 30)

#define STATUS_YBUF_EMPTY       (1 << 29)

#define STATUS_XBUF_EMPTY       (1 << 28)

#define STATUS_YBUF_FULL        (1 << 27)

#define STATUS_XBUF_FULL        (1 << 26)

#define STATUS_BUF_UND_RUN      (1 << 25)

#define STATUS_BUF_OVFL         (1 << 24)

#define STATUS_SDIO_INT_ACTIVE      (1 << 14)

#define STATUS_END_CMD_RESP     (1 << 13)

#define STATUS_WRITE_OP_DONE        (1 << 12)

#define STATUS_DATA_TRANS_DONE      (1 << 11)

#define STATUS_READ_OP_DONE     (1 << 11)

#define STATUS_WR_CRC_ERROR_CODE_MASK   (3 << 10)

#define STATUS_CARD_BUS_CLK_RUN     (1 << 8)

#define STATUS_BUF_READ_RDY     (1 << 7)

#define STATUS_BUF_WRITE_RDY        (1 << 6)

#define STATUS_RESP_CRC_ERR     (1 << 5)

#define STATUS_CRC_READ_ERR     (1 << 3)

#define STATUS_CRC_WRITE_ERR        (1 << 2)

#define STATUS_TIME_OUT_RESP        (1 << 1)

#define STATUS_TIME_OUT_READ        (1 << 0)

#define STATUS_ERR_MASK         0x2f

​

#define CMD_DAT_CONT_CMD_RESP_LONG_OFF  (1 << 12)

#define CMD_DAT_CONT_STOP_READWAIT  (1 << 11)

#define CMD_DAT_CONT_START_READWAIT (1 << 10)

#define CMD_DAT_CONT_BUS_WIDTH_4    (2 << 8)

#define CMD_DAT_CONT_INIT       (1 << 7)

#define CMD_DAT_CONT_WRITE      (1 << 4)

#define CMD_DAT_CONT_DATA_ENABLE    (1 << 3)

#define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0)

#define CMD_DAT_CONT_RESPONSE_136BIT    (2 << 0)

#define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0)

​

#define INT_SDIO_INT_WKP_EN     (1 << 18)

#define INT_CARD_INSERTION_WKP_EN   (1 << 17)

#define INT_CARD_REMOVAL_WKP_EN     (1 << 16)

#define INT_CARD_INSERTION_EN       (1 << 15)