uboot-phytec

/*

​

Ported to U-Boot  by Christian Pellegrin <chri@ascensit.com>

​

Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and

eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world

are GPL, so this is, of course, GPL.

​

*/

​

/* Generic NS8390 register definitions. */

/* This file is part of Donald Becker's 8390 drivers, and is distributed

   under the same license. Auto-loading of 8390.o only in v2.2 - Paul G.

   Some of these names and comments originated from the Crynwr

   packet drivers, which are distributed under the GPL. */

​

#ifndef _8390_h

#define _8390_h

​

/* Some generic ethernet register configurations. */

#define E8390_TX_IRQ_MASK   0xa /* For register EN0_ISR */

#define E8390_RX_IRQ_MASK   0x5

#define E8390_RXCONFIG      0x4 /* EN0_RXCR: broadcasts, no multicast,errors */

#define E8390_RXOFF     0x20    /* EN0_RXCR: Accept no packets */

#define E8390_TXCONFIG      0x00    /* EN0_TXCR: Normal transmit mode */

#define E8390_TXOFF     0x02    /* EN0_TXCR: Transmitter off */

​

/*  Register accessed at EN_CMD, the 8390 base addr.  */

#define E8390_STOP  0x01    /* Stop and reset the chip */

#define E8390_START 0x02    /* Start the chip, clear reset */

#define E8390_TRANS 0x04    /* Transmit a frame */

#define E8390_RREAD 0x08    /* Remote read */

#define E8390_RWRITE    0x10    /* Remote write  */

#define E8390_NODMA 0x20    /* Remote DMA */

#define E8390_PAGE0 0x00    /* Select page chip registers */

#define E8390_PAGE1 0x40    /* using the two high-order bits */

#define E8390_PAGE2 0x80    /* Page 3 is invalid. */

​

/*

 *  Only generate indirect loads given a machine that needs them.

 *      - removed AMIGA_PCMCIA from this list, handled as ISA io now

 */

​

#define n2k_inb(port)   (*((volatile unsigned char *)(port+CONFIG_DRIVER_NE2000_BASE)))

#define n2k_outb(val,port)  (*((volatile unsigned char *)(port+CONFIG_DRIVER_NE2000_BASE)) = val)

​

#define EI_SHIFT(x) (x)

​

#define E8390_CMD   EI_SHIFT(0x00)  /* The command register (for all pages) */

/* Page 0 register offsets. */

#define EN0_CLDALO  EI_SHIFT(0x01)  /* Low byte of current local dma addr  RD */

#define EN0_STARTPG EI_SHIFT(0x01)  /* Starting page of ring bfr WR */

#define EN0_CLDAHI  EI_SHIFT(0x02)  /* High byte of current local dma addr  RD */

#define EN0_STOPPG  EI_SHIFT(0x02)  /* Ending page +1 of ring bfr WR */

#define EN0_BOUNDARY    EI_SHIFT(0x03)  /* Boundary page of ring bfr RD WR */

#define EN0_TSR     EI_SHIFT(0x04)  /* Transmit status reg RD */

#define EN0_TPSR    EI_SHIFT(0x04)  /* Transmit starting page WR */

#define EN0_NCR     EI_SHIFT(0x05)  /* Number of collision reg RD */

#define EN0_TCNTLO  EI_SHIFT(0x05)  /* Low  byte of tx byte count WR */

#define EN0_FIFO    EI_SHIFT(0x06)  /* FIFO RD */

#define EN0_TCNTHI  EI_SHIFT(0x06)  /* High byte of tx byte count WR */

#define EN0_ISR     EI_SHIFT(0x07)  /* Interrupt status reg RD WR */

#define EN0_CRDALO  EI_SHIFT(0x08)  /* low byte of current remote dma address RD */