uboot-phytec

/* SPDX-License-Identifier: GPL-2.0+ */

/*

 * (C) Copyright 2011

 * eInfochips Ltd. <www.einfochips.com>

 * Written-by: Ajay Bhargav <contact@8051projects.net>

 *

 * (C) Copyright 2010

 * Marvell Semiconductor <www.marvell.com>

 * Contributor: Mahavir Jain <mjain@marvell.com>

 */

​

#ifndef __ARMADA100_FEC_H__

#define __ARMADA100_FEC_H__

​

#define PORT_NUM        0x0

​

/* RX & TX descriptor command */

#define BUF_OWNED_BY_DMA        (1<<31)

​

/* RX descriptor status */

#define RX_EN_INT               (1<<23)

#define RX_FIRST_DESC           (1<<17)

#define RX_LAST_DESC            (1<<16)

#define RX_ERROR                (1<<15)

​

/* TX descriptor command */

#define TX_EN_INT               (1<<23)

#define TX_GEN_CRC              (1<<22)

#define TX_ZERO_PADDING         (1<<18)

#define TX_FIRST_DESC           (1<<17)

#define TX_LAST_DESC            (1<<16)

#define TX_ERROR                (1<<15)

​

/* smi register */

#define SMI_BUSY                (1<<28) /* 0 - Write, 1 - Read  */

#define SMI_R_VALID             (1<<27) /* 0 - Write, 1 - Read  */

#define SMI_OP_W                (0<<26) /* Write operation      */

#define SMI_OP_R                (1<<26) /* Read operation */

​

#define HASH_ADD                0

#define HASH_DELETE             1

#define HASH_ADDR_TABLE_SIZE    0x4000  /* 16K (1/2K address - PCR_HS == 1) */

#define HOP_NUMBER              12

​

#define PHY_WAIT_ITERATIONS     1000    /* 1000 iterations * 10uS = 10mS max */

#define PHY_WAIT_MICRO_SECONDS  10

​

#define ETH_HW_IP_ALIGN         2   /* hw aligns IP header */

#define ETH_EXTRA_HEADER        (6+6+2+4)

                    /* dest+src addr+protocol id+crc */

#define MAX_PKT_SIZE            1536

​

​

/* Bit definitions of the SDMA Config Reg */

#define SDCR_BSZ_OFF            12

#define SDCR_BSZ8               (3<<SDCR_BSZ_OFF)

#define SDCR_BSZ4               (2<<SDCR_BSZ_OFF)

#define SDCR_BSZ2               (1<<SDCR_BSZ_OFF)

#define SDCR_BSZ1               (0<<SDCR_BSZ_OFF)

#define SDCR_BLMR               (1<<6)

#define SDCR_BLMT               (1<<7)

#define SDCR_RIFB               (1<<9)

#define SDCR_RC_OFF             2

#define SDCR_RC_MAX_RETRANS     (0xf << SDCR_RC_OFF)

​

/* SDMA_CMD */

#define SDMA_CMD_AT             (1<<31)

#define SDMA_CMD_TXDL           (1<<24)

#define SDMA_CMD_TXDH           (1<<23)

#define SDMA_CMD_AR             (1<<15)

#define SDMA_CMD_ERD            (1<<7)

​

​

/* Bit definitions of the Port Config Reg */

#define PCR_HS                  (1<<12)

#define PCR_EN                  (1<<7)

#define PCR_PM                  (1<<0)

​

/* Bit definitions of the Port Config Extend Reg */

#define PCXR_2BSM               (1<<28)

#define PCXR_DSCP_EN            (1<<21)

#define PCXR_MFL_1518           (0<<14)

#define PCXR_MFL_1536           (1<<14)

#define PCXR_MFL_2048           (2<<14)

#define PCXR_MFL_64K            (3<<14)

#define PCXR_FLP                (1<<11)

#define PCXR_PRIO_TX_OFF        3

#define PCXR_TX_HIGH_PRI        (7<<PCXR_PRIO_TX_OFF)

​

/*

 *  * Bit definitions of the Interrupt Cause Reg

 *   * and Interrupt MASK Reg is the same