uboot-phytec

/* SPDX-License-Identifier: GPL-2.0+ */

/*

 * Copyright 2014 Broadcom Corporation.

 */

​

#ifndef _BCM_SF2_ETH_GMAC_H_

#define _BCM_SF2_ETH_GMAC_H_

​

#define BCM_SF2_ETH_MAC_NAME    "gmac"

​

#ifndef ETHHW_PORT_INT

#define ETHHW_PORT_INT      8

#endif

​

#define GMAC0_REG_BASE          0x18042000

#define GMAC0_DEV_CTRL_ADDR     GMAC0_REG_BASE

#define GMAC0_INT_STATUS_ADDR       (GMAC0_REG_BASE + 0x020)

#define GMAC0_INTR_RECV_LAZY_ADDR   (GMAC0_REG_BASE + 0x100)

#define GMAC0_PHY_CTRL_ADDR     (GMAC0_REG_BASE + 0x188)

​

​

#define GMAC_DMA_PTR_OFFSET     0x04

#define GMAC_DMA_ADDR_LOW_OFFSET    0x08

#define GMAC_DMA_ADDR_HIGH_OFFSET   0x0c

#define GMAC_DMA_STATUS0_OFFSET     0x10

#define GMAC_DMA_STATUS1_OFFSET     0x14

​

#define GMAC0_DMA_TX_CTRL_ADDR      (GMAC0_REG_BASE + 0x200)

#define GMAC0_DMA_TX_PTR_ADDR \

        (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_PTR_OFFSET)

#define GMAC0_DMA_TX_ADDR_LOW_ADDR \

        (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_ADDR_LOW_OFFSET)

#define GMAC0_DMA_TX_ADDR_HIGH_ADDR \

        (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_ADDR_HIGH_OFFSET)

#define GMAC0_DMA_TX_STATUS0_ADDR \

        (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_STATUS0_OFFSET)

#define GMAC0_DMA_TX_STATUS1_ADDR \

        (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_STATUS1_OFFSET)

​

#define GMAC0_DMA_RX_CTRL_ADDR      (GMAC0_REG_BASE + 0x220)

#define GMAC0_DMA_RX_PTR_ADDR \

        (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_PTR_OFFSET)

#define GMAC0_DMA_RX_ADDR_LOW_ADDR \

        (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_ADDR_LOW_OFFSET)

#define GMAC0_DMA_RX_ADDR_HIGH_ADDR \

        (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_ADDR_HIGH_OFFSET)

#define GMAC0_DMA_RX_STATUS0_ADDR \

        (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_STATUS0_OFFSET)

#define GMAC0_DMA_RX_STATUS1_ADDR \

        (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_STATUS1_OFFSET)

​

#define UNIMAC0_CMD_CFG_ADDR        (GMAC0_REG_BASE + 0x808)

#define UNIMAC0_MAC_MSB_ADDR        (GMAC0_REG_BASE + 0x80c)

#define UNIMAC0_MAC_LSB_ADDR        (GMAC0_REG_BASE + 0x810)

#define UNIMAC0_FRM_LENGTH_ADDR     (GMAC0_REG_BASE + 0x814)

​

#define GMAC0_IRL_FRAMECOUNT_SHIFT  24

​

/* transmit channel control */

/* transmit enable */

#define D64_XC_XE       0x00000001

/* transmit suspend request */

#define D64_XC_SE       0x00000002