uboot-phytec

// SPDX-License-Identifier: GPL-2.0+

​

#include <common.h>

#include <malloc.h>

#include <net.h>

#include <netdev.h>

#include <pci.h>

​

#undef DEBUG_SROM

#undef DEBUG_SROM2

​

#undef UPDATE_SROM

​

/* PCI Registers.

 */

#define PCI_CFDA_PSM        0x43

​

#define CFRV_RN     0x000000f0  /* Revision Number */

​

#define WAKEUP      0x00        /* Power Saving Wakeup */

#define SLEEP       0x80        /* Power Saving Sleep Mode */

​

#define DC2114x_BRK 0x0020      /* CFRV break between DC21142 & DC21143 */

​

/* Ethernet chip registers.

 */

#define DE4X5_BMR   0x000       /* Bus Mode Register */

#define DE4X5_TPD   0x008       /* Transmit Poll Demand Reg */

#define DE4X5_RRBA  0x018       /* RX Ring Base Address Reg */

#define DE4X5_TRBA  0x020       /* TX Ring Base Address Reg */

#define DE4X5_STS   0x028       /* Status Register */

#define DE4X5_OMR   0x030       /* Operation Mode Register */

#define DE4X5_SICR  0x068       /* SIA Connectivity Register */

#define DE4X5_APROM 0x048       /* Ethernet Address PROM */

​

/* Register bits.

 */

#define BMR_SWR     0x00000001  /* Software Reset */

#define STS_TS      0x00700000  /* Transmit Process State */

#define STS_RS      0x000e0000  /* Receive Process State */

#define OMR_ST      0x00002000  /* Start/Stop Transmission Command */

#define OMR_SR      0x00000002  /* Start/Stop Receive */

#define OMR_PS      0x00040000  /* Port Select */

#define OMR_SDP     0x02000000  /* SD Polarity - MUST BE ASSERTED */

#define OMR_PM      0x00000080  /* Pass All Multicast */

​

/* Descriptor bits.

 */

#define R_OWN       0x80000000  /* Own Bit */

#define RD_RER      0x02000000  /* Receive End Of Ring */

#define RD_LS       0x00000100  /* Last Descriptor */

#define RD_ES       0x00008000  /* Error Summary */

#define TD_TER      0x02000000  /* Transmit End Of Ring */

#define T_OWN       0x80000000  /* Own Bit */

#define TD_LS       0x40000000  /* Last Segment */

#define TD_FS       0x20000000  /* First Segment */

#define TD_ES       0x00008000  /* Error Summary */

#define TD_SET      0x08000000  /* Setup Packet */

​

/* The EEPROM commands include the alway-set leading bit. */

#define SROM_WRITE_CMD  5

#define SROM_READ_CMD   6

#define SROM_ERASE_CMD  7