uboot-phytec

// SPDX-License-Identifier: GPL-2.0+

/*

 * (C) Copyright 2002

 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.

 */

​

#include <common.h>

#include <malloc.h>

#include <net.h>

#include <netdev.h>

#include <asm/io.h>

#include <pci.h>

#include <miiphy.h>

​

#undef DEBUG

​

    /* Ethernet chip registers.

     */

#define SCBStatus       0   /* Rx/Command Unit Status *Word* */

#define SCBIntAckByte       1   /* Rx/Command Unit STAT/ACK byte */

#define SCBCmd          2   /* Rx/Command Unit Command *Word* */

#define SCBIntrCtlByte      3   /* Rx/Command Unit Intr.Control Byte */

#define SCBPointer      4   /* General purpose pointer. */

#define SCBPort         8   /* Misc. commands and operands. */

#define SCBflash        12  /* Flash memory control. */

#define SCBeeprom       14  /* EEPROM memory control. */

#define SCBCtrlMDI      16  /* MDI interface control. */

#define SCBEarlyRx      20  /* Early receive byte count. */

#define SCBGenControl       28  /* 82559 General Control Register */

#define SCBGenStatus        29  /* 82559 General Status register */

​

    /* 82559 SCB status word defnitions

     */

#define SCB_STATUS_CX       0x8000  /* CU finished command (transmit) */

#define SCB_STATUS_FR       0x4000  /* frame received */

#define SCB_STATUS_CNA      0x2000  /* CU left active state */

#define SCB_STATUS_RNR      0x1000  /* receiver left ready state */

#define SCB_STATUS_MDI      0x0800  /* MDI read/write cycle done */

#define SCB_STATUS_SWI      0x0400  /* software generated interrupt */

#define SCB_STATUS_FCP      0x0100  /* flow control pause interrupt */

​

#define SCB_INTACK_MASK     0xFD00  /* all the above */

​

#define SCB_INTACK_TX       (SCB_STATUS_CX | SCB_STATUS_CNA)

#define SCB_INTACK_RX       (SCB_STATUS_FR | SCB_STATUS_RNR)

​

    /* System control block commands

     */

/* CU Commands */

#define CU_NOP          0x0000

#define CU_START        0x0010

#define CU_RESUME       0x0020

#define CU_STATSADDR        0x0040  /* Load Dump Statistics ctrs addr */

#define CU_SHOWSTATS        0x0050  /* Dump statistics counters. */

#define CU_ADDR_LOAD        0x0060  /* Base address to add to CU commands */

#define CU_DUMPSTATS        0x0070  /* Dump then reset stats counters. */

​

/* RUC Commands */

#define RUC_NOP         0x0000

#define RUC_START       0x0001

#define RUC_RESUME      0x0002

#define RUC_ABORT       0x0004

#define RUC_ADDR_LOAD       0x0006  /* (seems not to clear on acceptance) */

#define RUC_RESUMENR        0x0007

​

#define CU_CMD_MASK     0x00f0

#define RU_CMD_MASK     0x0007

​

#define SCB_M           0x0100  /* 0 = enable interrupt, 1 = disable */

#define SCB_SWI         0x0200  /* 1 - cause device to interrupt */

​

#define CU_STATUS_MASK      0x00C0

#define RU_STATUS_MASK      0x003C

​

#define RU_STATUS_IDLE      (0<<2)

#define RU_STATUS_SUS       (1<<2)

#define RU_STATUS_NORES     (2<<2)

#define RU_STATUS_READY     (4<<2)

#define RU_STATUS_NO_RBDS_SUS   ((1<<2)|(8<<2))

#define RU_STATUS_NO_RBDS_NORES ((2<<2)|(8<<2))

#define RU_STATUS_NO_RBDS_READY ((4<<2)|(8<<2))

​

    /* 82559 Port interface commands.

     */

#define I82559_RESET        0x00000000  /* Software reset */

#define I82559_SELFTEST     0x00000001  /* 82559 Selftest command */

#define I82559_SELECTIVE_RESET  0x00000002

#define I82559_DUMP     0x00000003

#define I82559_DUMP_WAKEUP  0x00000007

​

    /* 82559 Eeprom interface.

     */