uboot-phytec

// SPDX-License-Identifier: GPL-2.0+

/*

 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>

 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>

 * (C) Copyright 2008 Armadeus Systems nc

 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>

 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>

 */

​

#include <common.h>

#include <dm.h>

#include <environment.h>

#include <malloc.h>

#include <memalign.h>

#include <miiphy.h>

#include <net.h>

#include <netdev.h>

#include "fec_mxc.h"

​

#include <asm/io.h>

#include <linux/errno.h>

#include <linux/compiler.h>

​

#include <asm/arch/clock.h>

#include <asm/arch/imx-regs.h>

#include <asm/mach-imx/sys_proto.h>

​

DECLARE_GLOBAL_DATA_PTR;

​

/*

 * Timeout the transfer after 5 mS. This is usually a bit more, since

 * the code in the tightloops this timeout is used in adds some overhead.

 */

#define FEC_XFER_TIMEOUT    5000

​

/*

 * The standard 32-byte DMA alignment does not work on mx6solox, which requires

 * 64-byte alignment in the DMA RX FEC buffer.

 * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also

 * satisfies the alignment on other SoCs (32-bytes)

 */

#define FEC_DMA_RX_MINALIGN 64

​

#ifndef CONFIG_MII

#error "CONFIG_MII has to be defined!"

#endif

​

#ifndef CONFIG_FEC_XCV_TYPE

#define CONFIG_FEC_XCV_TYPE MII100

#endif

​

/*

 * The i.MX28 operates with packets in big endian. We need to swap them before

 * sending and after receiving.

 */

#ifdef CONFIG_MX28

#define CONFIG_FEC_MXC_SWAP_PACKET

#endif

​

#define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd))

​

/* Check various alignment issues at compile time */

#if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0))