uboot-phytec
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committed 83d290c56fa * frames in more than one BD. This is nothing to worry about, but the current/* SPDX-License-Identifier: GPL-2.0+ *//* * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com> * (C) Copyright 2008 Armadeus Systems, nc * (C) Copyright 2008 Eric Jarrige <eric.jarrige@armadeus.org> * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de> * * (C) Copyright 2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * This file is based on mpc4200fec.h * (C) Copyright Motorola, Inc., 2000 *//* Layout description of the FEC */struct ethernet_regs { /* [10:2]addr = 00 */ /* Control and status Registers (offset 000-1FF) */ uint32_t res0[1]; /* MBAR_ETH + 0x000 */ uint32_t ievent; /* MBAR_ETH + 0x004 */ uint32_t imask; /* MBAR_ETH + 0x008 */ uint32_t res1[1]; /* MBAR_ETH + 0x00C */ uint32_t r_des_active; /* MBAR_ETH + 0x010 */ uint32_t x_des_active; /* MBAR_ETH + 0x014 */ uint32_t res2[3]; /* MBAR_ETH + 0x018-20 */ uint32_t ecntrl; /* MBAR_ETH + 0x024 */ uint32_t res3[6]; /* MBAR_ETH + 0x028-03C */ uint32_t mii_data; /* MBAR_ETH + 0x040 */ uint32_t mii_speed; /* MBAR_ETH + 0x044 */ uint32_t res4[7]; /* MBAR_ETH + 0x048-60 */ uint32_t mib_control; /* MBAR_ETH + 0x064 */ uint32_t res5[7]; /* MBAR_ETH + 0x068-80 */ uint32_t r_cntrl; /* MBAR_ETH + 0x084 */ uint32_t res6[15]; /* MBAR_ETH + 0x088-C0 */ uint32_t x_cntrl; /* MBAR_ETH + 0x0C4 */ uint32_t res7[7]; /* MBAR_ETH + 0x0C8-E0 */ uint32_t paddr1; /* MBAR_ETH + 0x0E4 */ uint32_t paddr2; /* MBAR_ETH + 0x0E8 */ uint32_t op_pause; /* MBAR_ETH + 0x0EC */ uint32_t res8[10]; /* MBAR_ETH + 0x0F0-114 */ uint32_t iaddr1; /* MBAR_ETH + 0x118 */ uint32_t iaddr2; /* MBAR_ETH + 0x11C */ uint32_t gaddr1; /* MBAR_ETH + 0x120 */ uint32_t gaddr2; /* MBAR_ETH + 0x124 */ uint32_t res9[7]; /* MBAR_ETH + 0x128-140 */ uint32_t x_wmrk; /* MBAR_ETH + 0x144 */ uint32_t res10[1]; /* MBAR_ETH + 0x148 */ uint32_t r_bound; /* MBAR_ETH + 0x14C */ uint32_t r_fstart; /* MBAR_ETH + 0x150 */ uint32_t res11[11]; /* MBAR_ETH + 0x154-17C */ uint32_t erdsr; /* MBAR_ETH + 0x180 */ uint32_t etdsr; /* MBAR_ETH + 0x184 */ uint32_t emrbr; /* MBAR_ETH + 0x188 */