uboot-phytec

// SPDX-License-Identifier: GPL-2.0+

/*

 * Copyright 2012 Freescale Semiconductor, Inc.

 *  Andy Fleming <afleming@gmail.com>

 *  Roy Zang <tie-fei.zang@freescale.com>

 * Some part is taken from tsec.c

 */

#include <common.h>

#include <miiphy.h>

#include <phy.h>

#include <asm/io.h>

#include <fsl_memac.h>

#include <fm_eth.h>

​

#ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN

#define memac_out_32(a, v)  out_le32(a, v)

#define memac_clrbits_32(a, v)  clrbits_le32(a, v)

#define memac_setbits_32(a, v)  setbits_le32(a, v)

#else

#define memac_out_32(a, v)  out_be32(a, v)

#define memac_clrbits_32(a, v)  clrbits_be32(a, v)

#define memac_setbits_32(a, v)  setbits_be32(a, v)

#endif

​

static u32 memac_in_32(u32 *reg)

{

#ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN

    return in_le32(reg);

#else

    return in_be32(reg);

#endif

}

​

/*

 * Write value to the PHY for this device to the register at regnum, waiting

 * until the write is done before it returns.  All PHY configuration has to be

 * done through the TSEC1 MIIM regs

 */

int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,

            int regnum, u16 value)

{

    u32 mdio_ctl;

    struct memac_mdio_controller *regs = bus->priv;

    u32 c45 = 1; /* Default to 10G interface */

​

    if (dev_addr == MDIO_DEVAD_NONE) {

        c45 = 0; /* clause 22 */

        dev_addr = regnum & 0x1f;

        memac_clrbits_32(&regs->mdio_stat, MDIO_STAT_ENC);

    } else

        memac_setbits_32(&regs->mdio_stat, MDIO_STAT_ENC);

​

    /* Wait till the bus is free */

    while ((memac_in_32(&regs->mdio_stat)) & MDIO_STAT_BSY)

        ;

​

    /* Set the port and dev addr */

    mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);

    memac_out_32(&regs->mdio_ctl, mdio_ctl);

​

    /* Set the register address */

    if (c45)

        memac_out_32(&regs->mdio_addr, regnum & 0xffff);