uboot-phytec

/* SPDX-License-Identifier: GPL-2.0+ */

/*

 * Faraday FTGMAC100 Ethernet

 *

 * (C) Copyright 2010 Faraday Technology

 * Po-Yu Chuang <ratbert@faraday-tech.com>

 *

 * (C) Copyright 2010 Andes Technology

 * Macpaul Lin <macpaul@andestech.com>

 */

​

#ifndef __FTGMAC100_H

#define __FTGMAC100_H

​

/* The registers offset table of ftgmac100 */

struct ftgmac100 {

    unsigned int    isr;        /* 0x00 */

    unsigned int    ier;        /* 0x04 */

    unsigned int    mac_madr;   /* 0x08 */

    unsigned int    mac_ladr;   /* 0x0c */

    unsigned int    maht0;      /* 0x10 */

    unsigned int    maht1;      /* 0x14 */

    unsigned int    txpd;       /* 0x18 */

    unsigned int    rxpd;       /* 0x1c */

    unsigned int    txr_badr;   /* 0x20 */

    unsigned int    rxr_badr;   /* 0x24 */

    unsigned int    hptxpd;     /* 0x28 */

    unsigned int    hptxpd_badr;    /* 0x2c */

    unsigned int    itc;        /* 0x30 */

    unsigned int    aptc;       /* 0x34 */

    unsigned int    dblac;      /* 0x38 */

    unsigned int    dmafifos;   /* 0x3c */

    unsigned int    revr;       /* 0x40 */

    unsigned int    fear;       /* 0x44 */

    unsigned int    tpafcr;     /* 0x48 */

    unsigned int    rbsr;       /* 0x4c */

    unsigned int    maccr;      /* 0x50 */

    unsigned int    macsr;      /* 0x54 */

    unsigned int    tm;     /* 0x58 */

    unsigned int    resv1;      /* 0x5c */ /* not defined in spec */

    unsigned int    phycr;      /* 0x60 */

    unsigned int    phydata;    /* 0x64 */

    unsigned int    fcr;        /* 0x68 */

    unsigned int    bpr;        /* 0x6c */

    unsigned int    wolcr;      /* 0x70 */

    unsigned int    wolsr;      /* 0x74 */

    unsigned int    wfcrc;      /* 0x78 */

    unsigned int    resv2;      /* 0x7c */ /* not defined in spec */

    unsigned int    wfbm1;      /* 0x80 */

    unsigned int    wfbm2;      /* 0x84 */

    unsigned int    wfbm3;      /* 0x88 */

    unsigned int    wfbm4;      /* 0x8c */

    unsigned int    nptxr_ptr;  /* 0x90 */

    unsigned int    hptxr_ptr;  /* 0x94 */

    unsigned int    rxr_ptr;    /* 0x98 */

    unsigned int    resv3;      /* 0x9c */ /* not defined in spec */

    unsigned int    tx;     /* 0xa0 */

    unsigned int    tx_mcol_scol;   /* 0xa4 */

    unsigned int    tx_ecol_fail;   /* 0xa8 */

    unsigned int    tx_lcol_und;    /* 0xac */

    unsigned int    rx;     /* 0xb0 */

    unsigned int    rx_bc;      /* 0xb4 */

    unsigned int    rx_mc;      /* 0xb8 */

    unsigned int    rx_pf_aep;  /* 0xbc */

    unsigned int    rx_runt;    /* 0xc0 */

    unsigned int    rx_crcer_ftl;   /* 0xc4 */

    unsigned int    rx_col_lost;    /* 0xc8 */

};

​

/*

 * Interrupt status register & interrupt enable register

 */

#define FTGMAC100_INT_RPKT_BUF      (1 << 0)

#define FTGMAC100_INT_RPKT_FIFO     (1 << 1)

#define FTGMAC100_INT_NO_RXBUF      (1 << 2)

#define FTGMAC100_INT_RPKT_LOST     (1 << 3)

#define FTGMAC100_INT_XPKT_ETH      (1 << 4)

#define FTGMAC100_INT_XPKT_FIFO     (1 << 5)

#define FTGMAC100_INT_NO_NPTXBUF    (1 << 6)

#define FTGMAC100_INT_XPKT_LOST     (1 << 7)

#define FTGMAC100_INT_AHB_ERR       (1 << 8)

#define FTGMAC100_INT_PHYSTS_CHG    (1 << 9)

#define FTGMAC100_INT_NO_HPTXBUF    (1 << 10)

​

/*

 * Interrupt timer control register

 */

#define FTGMAC100_ITC_RXINT_CNT(x)  (((x) & 0xf) << 0)

#define FTGMAC100_ITC_RXINT_THR(x)  (((x) & 0x7) << 4)

#define FTGMAC100_ITC_RXINT_TIME_SEL    (1 << 7)

#define FTGMAC100_ITC_TXINT_CNT(x)  (((x) & 0xf) << 8)

#define FTGMAC100_ITC_TXINT_THR(x)  (((x) & 0x7) << 12)