Source
static int ftmac110_mdio_write(struct mii_dev *bus, int addr, int devad,
// SPDX-License-Identifier: GPL-2.0+
/*
* Faraday 10/100Mbps Ethernet Controller
*
* (C) Copyright 2013 Faraday Technology
* Dante Su <dantesu@faraday-tech.com>
*/
/* 500 ms */
/* 500 ms */
/* 4 sec */
/*
* FTMAC110 DMA design issue
*
* Its DMA engine has a weird restriction that its Rx DMA engine
* accepts only 16-bits aligned address, 32-bits aligned is not
* acceptable. However this restriction does not apply to Tx DMA.
*
* Conclusion:
* (1) Tx DMA Buffer Address:
* 1 bytes aligned: Invalid
* 2 bytes aligned: O.K
* 4 bytes aligned: O.K (-> u-boot ZeroCopy is possible)
* (2) Rx DMA Buffer Address:
* 1 bytes aligned: Invalid
* 2 bytes aligned: O.K
* 4 bytes aligned: Invalid
*/
struct ftmac110_chip {
void __iomem *regs;
uint32_t imr;
uint32_t maccr;
uint32_t lnkup;
uint32_t phy_addr;
struct ftmac110_desc *rxd;
ulong rxd_dma;
uint32_t rxd_idx;
struct ftmac110_desc *txd;
ulong txd_dma;
uint32_t txd_idx;
};
static int ftmac110_reset(struct eth_device *dev);
static uint16_t mdio_read(struct eth_device *dev,
uint8_t phyaddr, uint8_t phyreg)
{
struct ftmac110_chip *chip = dev->priv;
struct ftmac110_regs *regs = chip->regs;
uint32_t tmp, ts;
uint16_t ret = 0xffff;
tmp = PHYCR_READ
| (phyaddr << PHYCR_ADDR_SHIFT)
| (phyreg << PHYCR_REG_SHIFT);
writel(tmp, ®s->phycr);
for (ts = get_timer(0); get_timer(ts) < CFG_MDIORD_TIMEOUT; ) {
tmp = readl(®s->phycr);
if (tmp & PHYCR_READ)
continue;
break;
}
if (tmp & PHYCR_READ)
printf("ftmac110: mdio read timeout\n");
else
ret = (uint16_t)(tmp & 0xffff);