uboot-phytec

/* SPDX-License-Identifier: GPL-2.0+ */

/*

 * Faraday 10/100Mbps Ethernet Controller

 *

 * (C) Copyright 2013 Faraday Technology

 * Dante Su <dantesu@faraday-tech.com>

 */

​

#ifndef _FTMAC110_H

#define _FTMAC110_H

​

struct ftmac110_regs {

    uint32_t isr;    /* 0x00: Interrups Status Register */

    uint32_t imr;    /* 0x04: Interrupt Mask Register */

    uint32_t mac[2]; /* 0x08: MAC Address */

    uint32_t mht[2]; /* 0x10: Multicast Hash Table Register */

    uint32_t txpd;   /* 0x18: Tx Poll Demand Register */

    uint32_t rxpd;   /* 0x1c: Rx Poll Demand Register */

    uint32_t txba;   /* 0x20: Tx Ring Base Address Register */

    uint32_t rxba;   /* 0x24: Rx Ring Base Address Register */

    uint32_t itc;    /* 0x28: Interrupt Timer Control Register */

    uint32_t aptc;   /* 0x2C: Automatic Polling Timer Control Register */

    uint32_t dblac;  /* 0x30: DMA Burst Length&Arbitration Control */

    uint32_t revr;   /* 0x34: Revision Register */

    uint32_t fear;   /* 0x38: Feature Register */

    uint32_t rsvd[19];

    uint32_t maccr;  /* 0x88: MAC Control Register */

    uint32_t macsr;  /* 0x8C: MAC Status Register */

    uint32_t phycr;  /* 0x90: PHY Control Register */

    uint32_t phydr;  /* 0x94: PHY Data Register */

    uint32_t fcr;    /* 0x98: Flow Control Register */

    uint32_t bpr;    /* 0x9C: Back Pressure Register */

};

​

/*

 * Interrupt status/mask register(ISR/IMR) bits

 */

#define ISR_ALL          0x3ff

#define ISR_PHYSTCHG     (1 << 9) /* phy status change */

#define ISR_AHBERR       (1 << 8) /* bus error */

#define ISR_RXLOST       (1 << 7) /* rx lost */

#define ISR_RXFIFO       (1 << 6) /* rx to fifo */

#define ISR_TXLOST       (1 << 5) /* tx lost */

#define ISR_TXOK         (1 << 4) /* tx to ethernet */

#define ISR_NOTXBUF      (1 << 3) /* out of tx buffer */

#define ISR_TXFIFO       (1 << 2) /* tx to fifo */

#define ISR_NORXBUF      (1 << 1) /* out of rx buffer */

#define ISR_RXOK         (1 << 0) /* rx to buffer */

​

/*

 * MACCR control bits

 */

#define MACCR_100M       (1 << 18) /* 100Mbps mode */

#define MACCR_RXBCST     (1 << 17) /* rx broadcast packet */

#define MACCR_RXMCST     (1 << 16) /* rx multicast packet */

#define MACCR_FD         (1 << 15) /* full duplex */

#define MACCR_CRCAPD     (1 << 14) /* tx crc append */

#define MACCR_RXALL      (1 << 12) /* rx all packets */

#define MACCR_RXFTL      (1 << 11) /* rx packet even it's > 1518 byte */

#define MACCR_RXRUNT     (1 << 10) /* rx packet even it's < 64 byte */

#define MACCR_RXMCSTHT   (1 << 9)  /* rx multicast hash table */

#define MACCR_RXEN       (1 << 8)  /* rx enable */

#define MACCR_RXINHDTX   (1 << 6)  /* rx in half duplex tx */