uboot-phytec

/* SPDX-License-Identifier: GPL-2.0+ */

/*

 * (C) Copyright 2009

 * Marvell Semiconductor <www.marvell.com>

 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>

 *

 * based on - Driver for MV64360X ethernet ports

 * Copyright (C) 2002 rabeeh@galileo.co.il

 */

​

#ifndef __MVGBE_H__

#define __MVGBE_H__

​

/* PHY_BASE_ADR is board specific and can be configured */

#if defined (CONFIG_PHY_BASE_ADR)

#define PHY_BASE_ADR        CONFIG_PHY_BASE_ADR

#else

#define PHY_BASE_ADR        0x08    /* default phy base addr */

#endif

​

/* Constants */

#define INT_CAUSE_UNMASK_ALL        0x0007ffff

#define INT_CAUSE_UNMASK_ALL_EXT    0x0011ffff

#define MRU_MASK            0xfff1ffff

#define PHYADR_MASK         0x0000001f

#define PHYREG_MASK         0x0000001f

#define QTKNBKT_DEF_VAL         0x3fffffff

#define QMTBS_DEF_VAL           0x000003ff

#define QTKNRT_DEF_VAL          0x0000fcff

#define RXUQ    0 /* Used Rx queue */

#define TXUQ    0 /* Used Rx queue */

​

#define to_mvgbe(_d) container_of(_d, struct mvgbe_device, dev)

#define MVGBE_REG_WR(adr, val)      writel(val, &adr)

#define MVGBE_REG_RD(adr)       readl(&adr)

#define MVGBE_REG_BITS_RESET(adr, val)  writel(readl(&adr) & ~(val), &adr)

#define MVGBE_REG_BITS_SET(adr, val)    writel(readl(&adr) | val, &adr)

​

/* Default port configuration value */

#define PRT_CFG_VAL         ( \

    MVGBE_UCAST_MOD_NRML        | \

    MVGBE_DFLT_RXQ(RXUQ)        | \

    MVGBE_DFLT_RX_ARPQ(RXUQ)    | \

    MVGBE_RX_BC_IF_NOT_IP_OR_ARP    | \

    MVGBE_RX_BC_IF_IP       | \

    MVGBE_RX_BC_IF_ARP      | \

    MVGBE_CPTR_TCP_FRMS_DIS     | \

    MVGBE_CPTR_UDP_FRMS_DIS     | \

    MVGBE_DFLT_RX_TCPQ(RXUQ)    | \

    MVGBE_DFLT_RX_UDPQ(RXUQ)    | \

    MVGBE_DFLT_RX_BPDUQ(RXUQ))

​

/* Default port extend configuration value */

#define PORT_CFG_EXTEND_VALUE       \

    MVGBE_SPAN_BPDU_PACKETS_AS_NORMAL   | \

    MVGBE_PARTITION_DIS     | \

    MVGBE_TX_CRC_GENERATION_EN

​

#define GT_MVGBE_IPG_INT_RX(value)  ((value & 0x3fff) << 8)

​

/* Default sdma control value */

#define PORT_SDMA_CFG_VALUE     ( \

    MVGBE_RX_BURST_SIZE_16_64BIT    | \

    MVGBE_BLM_RX_NO_SWAP        | \

    MVGBE_BLM_TX_NO_SWAP        | \

    GT_MVGBE_IPG_INT_RX(RXUQ)   | \

    MVGBE_TX_BURST_SIZE_16_64BIT)

​

/* Default port serial control value */

#ifndef PORT_SERIAL_CONTROL_VALUE

#define PORT_SERIAL_CONTROL_VALUE       ( \

    MVGBE_FORCE_LINK_PASS           | \

    MVGBE_DIS_AUTO_NEG_FOR_DUPLX        | \

    MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL    | \

    MVGBE_ADV_NO_FLOW_CTRL          | \

    MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \

    MVGBE_FORCE_BP_MODE_NO_JAM      | \

    (1 << 9) /* Reserved bit has to be 1 */ | \

    MVGBE_DO_NOT_FORCE_LINK_FAIL        | \

    MVGBE_EN_AUTO_NEG_SPEED_GMII        | \

    MVGBE_DTE_ADV_0             | \

    MVGBE_MIIPHY_MAC_MODE           | \

    MVGBE_AUTO_NEG_NO_CHANGE        | \

    MVGBE_MAX_RX_PACKET_1552BYTE        | \

    MVGBE_CLR_EXT_LOOPBACK          | \

    MVGBE_SET_FULL_DUPLEX_MODE      | \

    MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX)

#endif

​

/* Tx WRR confoguration macros */

#define PORT_MAX_TRAN_UNIT  0x24    /* MTU register (default) 9KByte */

#define PORT_MAX_TOKEN_BUCKET_SIZE  0x_FFFF /* PMTBS reg (default) */