uboot-phytec

/* SPDX-License-Identifier: GPL-2.0+ */

/*

 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>

 *

 * Intel Platform Controller Hub EG20T (codename Topcliff) GMAC Driver

 * Adapted from linux drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h

 */

​

#ifndef _PCH_GBE_H_

#define _PCH_GBE_H_

​

#define PCH_GBE_TIMEOUT     (3 * CONFIG_SYS_HZ)

​

#define PCH_GBE_DESC_NUM    4

#define PCH_GBE_ALIGN_SIZE  64

​

/*

 * Topcliff GBE MAC supports receiving ethernet frames with normal frame size

 * (64-1518 bytes) as well as up to 10318 bytes, however it does not have a

 * register bit to turn off receiving 'jumbo frame', so we have to allocate

 * our own buffer to store the received frames instead of using U-Boot's own.

 */

#define PCH_GBE_RX_FRAME_LEN    ROUND(10318, PCH_GBE_ALIGN_SIZE)

​

/* Interrupt Status */

/* Interrupt Status Hold */

/* Interrupt Enable */

#define PCH_GBE_INT_RX_DMA_CMPLT    0x00000001

#define PCH_GBE_INT_RX_VALID        0x00000002

#define PCH_GBE_INT_RX_FRAME_ERR    0x00000004

#define PCH_GBE_INT_RX_FIFO_ERR     0x00000008

#define PCH_GBE_INT_RX_DMA_ERR      0x00000010

#define PCH_GBE_INT_RX_DSC_EMP      0x00000020

#define PCH_GBE_INT_TX_CMPLT        0x00000100

#define PCH_GBE_INT_TX_DMA_CMPLT    0x00000200

#define PCH_GBE_INT_TX_FIFO_ERR     0x00000400

#define PCH_GBE_INT_TX_DMA_ERR      0x00000800

#define PCH_GBE_INT_PAUSE_CMPLT     0x00001000

#define PCH_GBE_INT_MIIM_CMPLT      0x00010000

#define PCH_GBE_INT_PHY_INT     0x00100000

#define PCH_GBE_INT_WOL_DET     0x01000000

#define PCH_GBE_INT_TCPIP_ERR       0x10000000

​

/* Mode */

#define PCH_GBE_MODE_MII_ETHER      0x00000000

#define PCH_GBE_MODE_GMII_ETHER     0x80000000

#define PCH_GBE_MODE_HALF_DUPLEX    0x00000000

#define PCH_GBE_MODE_FULL_DUPLEX    0x40000000

#define PCH_GBE_MODE_FR_BST     0x04000000

​

/* Reset */

#define PCH_GBE_ALL_RST         0x80000000

#define PCH_GBE_TX_RST          0x00008000

#define PCH_GBE_RX_RST          0x00004000

​

/* TCP/IP Accelerator Control */

#define PCH_GBE_EX_LIST_EN      0x00000008

#define PCH_GBE_RX_TCPIPACC_OFF     0x00000004

#define PCH_GBE_TX_TCPIPACC_EN      0x00000002

#define PCH_GBE_RX_TCPIPACC_EN      0x00000001

​

/* MAC RX Enable */

#define PCH_GBE_MRE_MAC_RX_EN       0x00000001

​

/* RX Flow Control */

#define PCH_GBE_FL_CTRL_EN      0x80000000

​

/* RX Mode */

#define PCH_GBE_ADD_FIL_EN      0x80000000

#define PCH_GBE_MLT_FIL_EN      0x40000000

#define PCH_GBE_RH_ALM_EMP_4        0x00000000

#define PCH_GBE_RH_ALM_EMP_8        0x00004000

#define PCH_GBE_RH_ALM_EMP_16       0x00008000

#define PCH_GBE_RH_ALM_EMP_32       0x0000c000

#define PCH_GBE_RH_ALM_FULL_4       0x00000000

#define PCH_GBE_RH_ALM_FULL_8       0x00001000

#define PCH_GBE_RH_ALM_FULL_16      0x00002000

#define PCH_GBE_RH_ALM_FULL_32      0x00003000

#define PCH_GBE_RH_RD_TRG_4     0x00000000

#define PCH_GBE_RH_RD_TRG_8     0x00000200

#define PCH_GBE_RH_RD_TRG_16        0x00000400

#define PCH_GBE_RH_RD_TRG_32        0x00000600

#define PCH_GBE_RH_RD_TRG_64        0x00000800

#define PCH_GBE_RH_RD_TRG_128       0x00000a00

#define PCH_GBE_RH_RD_TRG_256       0x00000c00

#define PCH_GBE_RH_RD_TRG_512       0x00000e00

​

/* TX Mode */

#define PCH_GBE_TM_NO_RTRY      0x80000000

#define PCH_GBE_TM_LONG_PKT     0x40000000

#define PCH_GBE_TM_ST_AND_FD        0x20000000

#define PCH_GBE_TM_SHORT_PKT        0x10000000