uboot-phytec

// SPDX-License-Identifier: GPL-2.0+

/*

 * Broadcom PHY drivers

 *

 * Copyright 2010-2011 Freescale Semiconductor, Inc.

 * author Andy Fleming

 */

#include <config.h>

#include <common.h>

#include <phy.h>

​

/* Broadcom BCM54xx -- taken from linux sungem_phy */

#define MIIM_BCM54xx_AUXCNTL            0x18

#define MIIM_BCM54xx_AUXCNTL_ENCODE(val) (((val & 0x7) << 12)|(val & 0x7))

#define MIIM_BCM54xx_AUXSTATUS          0x19

#define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK    0x0700

#define MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT   8

​

#define MIIM_BCM54XX_SHD            0x1c

#define MIIM_BCM54XX_SHD_WRITE          0x8000

#define MIIM_BCM54XX_SHD_VAL(x)         ((x & 0x1f) << 10)

#define MIIM_BCM54XX_SHD_DATA(x)        ((x & 0x3ff) << 0)

#define MIIM_BCM54XX_SHD_WR_ENCODE(val, data)   \

    (MIIM_BCM54XX_SHD_WRITE | MIIM_BCM54XX_SHD_VAL(val) | \

     MIIM_BCM54XX_SHD_DATA(data))

​

#define MIIM_BCM54XX_EXP_DATA       0x15    /* Expansion register data */

#define MIIM_BCM54XX_EXP_SEL        0x17    /* Expansion register select */

#define MIIM_BCM54XX_EXP_SEL_SSD    0x0e00  /* Secondary SerDes select */

#define MIIM_BCM54XX_EXP_SEL_ER     0x0f00  /* Expansion register select */

​

#define MIIM_BCM_AUXCNTL_SHDWSEL_MISC   0x0007

#define MIIM_BCM_AUXCNTL_ACTL_SMDSP_EN  0x0800

​

#define MIIM_BCM_CHANNEL_WIDTH    0x2000

​

static void bcm_phy_write_misc(struct phy_device *phydev,

                   u16 reg, u16 chl, u16 value)

{

    int reg_val;

​

    phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL,

          MIIM_BCM_AUXCNTL_SHDWSEL_MISC);

​

    reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL);

    reg_val |= MIIM_BCM_AUXCNTL_ACTL_SMDSP_EN;

    phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, reg_val);

​

    reg_val = (chl * MIIM_BCM_CHANNEL_WIDTH) | reg;

    phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL, reg_val);

​

    phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA, value);

}

​

/* Broadcom BCM5461S */

static int bcm5461_config(struct phy_device *phydev)

{

    genphy_config_aneg(phydev);

​

    phy_reset(phydev);

​

    return 0;

}

​

static int bcm54xx_parse_status(struct phy_device *phydev)

{

    unsigned int mii_reg;

​

    mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXSTATUS);

​

    switch ((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >>

            MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT) {

    case 1:

        phydev->duplex = DUPLEX_HALF;

        phydev->speed = SPEED_10;

        break;

    case 2:

        phydev->duplex = DUPLEX_FULL;

        phydev->speed = SPEED_10;

        break;

    case 3:

        phydev->duplex = DUPLEX_HALF;

        phydev->speed = SPEED_100;

        break;

    case 5:

        phydev->duplex = DUPLEX_FULL;

        phydev->speed = SPEED_100;

        break;

    case 6:

        phydev->duplex = DUPLEX_HALF;

        phydev->speed = SPEED_1000;

        break;