uboot-phytec

// SPDX-License-Identifier: GPL-2.0+

/*

 * Copyright (C) 2011 Michal Simek <monstr@monstr.eu>

 * Copyright (C) 2011 PetaLogix

 * Copyright (C) 2010 Xilinx, Inc. All rights reserved.

 */

​

#include <config.h>

#include <common.h>

#include <dm.h>

#include <net.h>

#include <malloc.h>

#include <asm/io.h>

#include <phy.h>

#include <miiphy.h>

#include <wait_bit.h>

​

DECLARE_GLOBAL_DATA_PTR;

​

/* Link setup */

#define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */

#define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */

#define XAE_EMMC_LINKSPD_100    0x40000000 /* Link Speed mask for 100 Mbit */

#define XAE_EMMC_LINKSPD_1000   0x80000000 /* Link Speed mask for 1000 Mbit */

​

/* Interrupt Status/Enable/Mask Registers bit definitions */

#define XAE_INT_RXRJECT_MASK    0x00000008 /* Rx frame rejected */

#define XAE_INT_MGTRDY_MASK 0x00000080 /* MGT clock Lock */

​

/* Receive Configuration Word 1 (RCW1) Register bit definitions */

#define XAE_RCW1_RX_MASK    0x10000000 /* Receiver enable */

​

/* Transmitter Configuration (TC) Register bit definitions */

#define XAE_TC_TX_MASK      0x10000000 /* Transmitter enable */

​

#define XAE_UAW1_UNICASTADDR_MASK   0x0000FFFF

​

/* MDIO Management Configuration (MC) Register bit definitions */

#define XAE_MDIO_MC_MDIOEN_MASK     0x00000040 /* MII management enable*/

​

/* MDIO Management Control Register (MCR) Register bit definitions */

#define XAE_MDIO_MCR_PHYAD_MASK     0x1F000000 /* Phy Address Mask */

#define XAE_MDIO_MCR_PHYAD_SHIFT    24     /* Phy Address Shift */

#define XAE_MDIO_MCR_REGAD_MASK     0x001F0000 /* Reg Address Mask */

#define XAE_MDIO_MCR_REGAD_SHIFT    16     /* Reg Address Shift */

#define XAE_MDIO_MCR_OP_READ_MASK   0x00008000 /* Op Code Read Mask */

#define XAE_MDIO_MCR_OP_WRITE_MASK  0x00004000 /* Op Code Write Mask */

#define XAE_MDIO_MCR_INITIATE_MASK  0x00000800 /* Ready Mask */

#define XAE_MDIO_MCR_READY_MASK     0x00000080 /* Ready Mask */

​

#define XAE_MDIO_DIV_DFT    29  /* Default MDIO clock divisor */

​

#define XAXIDMA_BD_STS_ACTUAL_LEN_MASK  0x007FFFFF /* Actual len */

​

/* DMA macros */

/* Bitmasks of XAXIDMA_CR_OFFSET register */

#define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */

#define XAXIDMA_CR_RESET_MASK   0x00000004 /* Reset DMA engine */

​

/* Bitmasks of XAXIDMA_SR_OFFSET register */

#define XAXIDMA_HALTED_MASK 0x00000001  /* DMA channel halted */

​

/* Bitmask for interrupts */

#define XAXIDMA_IRQ_IOC_MASK    0x00001000 /* Completion intr */

#define XAXIDMA_IRQ_DELAY_MASK  0x00002000 /* Delay interrupt */

#define XAXIDMA_IRQ_ALL_MASK    0x00007000 /* All interrupts */

​

/* Bitmasks of XAXIDMA_BD_CTRL_OFFSET register */

#define XAXIDMA_BD_CTRL_TXSOF_MASK  0x08000000 /* First tx packet */

#define XAXIDMA_BD_CTRL_TXEOF_MASK  0x04000000 /* Last tx packet */

​

#define DMAALIGN    128

​

static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN)));

​

/* Reflect dma offsets */

struct axidma_reg {

    u32 control; /* DMACR */

    u32 status; /* DMASR */

    u32 current; /* CURDESC low 32 bit */

    u32 current_hi; /* CURDESC high 32 bit */

    u32 tail; /* TAILDESC low 32 bit */

    u32 tail_hi; /* TAILDESC high 32 bit */

};

​

/* Private driver structures */

struct axidma_priv {

    struct axidma_reg *dmatx;

    struct axidma_reg *dmarx;

    int phyaddr;

    struct axi_regs *iobase;

    phy_interface_t interface;