Source
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* axienet_dma_write - Memory mapped Axi DMA register Buffer Descriptor write.
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2011 Michal Simek <monstr@monstr.eu>
* Copyright (C) 2011 PetaLogix
* Copyright (C) 2010 Xilinx, Inc. All rights reserved.
*/
DECLARE_GLOBAL_DATA_PTR;
/* Link setup */
/* Link speed */
/* Link Speed mask for 10 Mbit */
/* Link Speed mask for 100 Mbit */
/* Link Speed mask for 1000 Mbit */
/* Interrupt Status/Enable/Mask Registers bit definitions */
/* Rx frame rejected */
/* MGT clock Lock */
/* Receive Configuration Word 1 (RCW1) Register bit definitions */
/* Receiver enable */
/* Transmitter Configuration (TC) Register bit definitions */
/* Transmitter enable */
/* MDIO Management Configuration (MC) Register bit definitions */
/* MII management enable*/
/* MDIO Management Control Register (MCR) Register bit definitions */
/* Phy Address Mask */
/* Phy Address Shift */
/* Reg Address Mask */
/* Reg Address Shift */
/* Op Code Read Mask */
/* Op Code Write Mask */
/* Ready Mask */
/* Ready Mask */
/* Default MDIO clock divisor */
/* Actual len */
/* DMA macros */
/* Bitmasks of XAXIDMA_CR_OFFSET register */
/* Start/stop DMA channel */
/* Reset DMA engine */
/* Bitmasks of XAXIDMA_SR_OFFSET register */
/* DMA channel halted */
/* Bitmask for interrupts */
/* Completion intr */
/* Delay interrupt */
/* All interrupts */
/* Bitmasks of XAXIDMA_BD_CTRL_OFFSET register */
/* First tx packet */
/* Last tx packet */
static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN)));
/* Reflect dma offsets */
struct axidma_reg {
u32 control; /* DMACR */
u32 status; /* DMASR */
u32 current; /* CURDESC low 32 bit */
u32 current_hi; /* CURDESC high 32 bit */
u32 tail; /* TAILDESC low 32 bit */
u32 tail_hi; /* TAILDESC high 32 bit */
};
/* Private driver structures */
struct axidma_priv {
struct axidma_reg *dmatx;
struct axidma_reg *dmarx;
int phyaddr;
struct axi_regs *iobase;
phy_interface_t interface;