uboot-phytec

// SPDX-License-Identifier: GPL-2.0+

/*

 * (C) Copyright 2007-2009 Michal Simek

 * (C) Copyright 2003 Xilinx Inc.

 *

 * Michal SIMEK <monstr@monstr.eu>

 */

​

#include <common.h>

#include <net.h>

#include <config.h>

#include <dm.h>

#include <console.h>

#include <malloc.h>

#include <asm/io.h>

#include <phy.h>

#include <miiphy.h>

#include <fdtdec.h>

#include <linux/errno.h>

#include <linux/kernel.h>

#include <asm/io.h>

​

DECLARE_GLOBAL_DATA_PTR;

​

#define ENET_ADDR_LENGTH    6

#define ETH_FCS_LEN     4 /* Octets in the FCS */

​

/* Xmit complete */

#define XEL_TSR_XMIT_BUSY_MASK      0x00000001UL

/* Xmit interrupt enable bit */

#define XEL_TSR_XMIT_IE_MASK        0x00000008UL

/* Program the MAC address */

#define XEL_TSR_PROGRAM_MASK        0x00000002UL

/* define for programming the MAC address into the EMAC Lite */

#define XEL_TSR_PROG_MAC_ADDR   (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)

​

/* Transmit packet length upper byte */

#define XEL_TPLR_LENGTH_MASK_HI     0x0000FF00UL

/* Transmit packet length lower byte */

#define XEL_TPLR_LENGTH_MASK_LO     0x000000FFUL

​

/* Recv complete */

#define XEL_RSR_RECV_DONE_MASK      0x00000001UL

/* Recv interrupt enable bit */

#define XEL_RSR_RECV_IE_MASK        0x00000008UL

​

/* MDIO Address Register Bit Masks */

#define XEL_MDIOADDR_REGADR_MASK  0x0000001F    /* Register Address */

#define XEL_MDIOADDR_PHYADR_MASK  0x000003E0    /* PHY Address */

#define XEL_MDIOADDR_PHYADR_SHIFT 5

#define XEL_MDIOADDR_OP_MASK      0x00000400    /* RD/WR Operation */

​

/* MDIO Write Data Register Bit Masks */

#define XEL_MDIOWR_WRDATA_MASK    0x0000FFFF    /* Data to be Written */

​

/* MDIO Read Data Register Bit Masks */

#define XEL_MDIORD_RDDATA_MASK    0x0000FFFF    /* Data to be Read */

​

/* MDIO Control Register Bit Masks */

#define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001    /* MDIO Status Mask */

#define XEL_MDIOCTRL_MDIOEN_MASK  0x00000008    /* MDIO Enable */

​

struct emaclite_regs {