uboot-phytec

// SPDX-License-Identifier: GPL-2.0+

/*

 * Meson G12A USB3+PCIE Combo PHY driver

 *

 * Copyright (C) 2018 Martin Blumenstingl <martin.blumenstingl@googlemail.com>

 * Copyright (C) 2019 BayLibre, SAS

 * Author: Neil Armstrong <narmstron@baylibre.com>

 */

​

#include <common.h>

#include <clk.h>

#include <dm.h>

#include <regmap.h>

#include <errno.h>

#include <asm/io.h>

#include <reset.h>

#include <bitfield.h>

#include <generic-phy.h>

​

#include <linux/bitops.h>

#include <linux/compat.h>

#include <linux/bitfield.h>

​

#define PHY_R0                          0x00

    #define PHY_R0_PCIE_POWER_STATE             GENMASK(4, 0)

    #define PHY_R0_PCIE_USB3_SWITCH             GENMASK(6, 5)

​

#define PHY_R1                          0x04

    #define PHY_R1_PHY_TX1_TERM_OFFSET          GENMASK(4, 0)

    #define PHY_R1_PHY_TX0_TERM_OFFSET          GENMASK(9, 5)

    #define PHY_R1_PHY_RX1_EQ               GENMASK(12, 10)

    #define PHY_R1_PHY_RX0_EQ               GENMASK(15, 13)

    #define PHY_R1_PHY_LOS_LEVEL                GENMASK(20, 16)

    #define PHY_R1_PHY_LOS_BIAS             GENMASK(23, 21)

    #define PHY_R1_PHY_REF_CLKDIV2              BIT(24)

    #define PHY_R1_PHY_MPLL_MULTIPLIER          GENMASK(31, 25)

​

#define PHY_R2                          0x08

    #define PHY_R2_PCS_TX_DEEMPH_GEN2_6DB           GENMASK(5, 0)

    #define PHY_R2_PCS_TX_DEEMPH_GEN2_3P5DB         GENMASK(11, 6)

    #define PHY_R2_PCS_TX_DEEMPH_GEN1           GENMASK(17, 12)

    #define PHY_R2_PHY_TX_VBOOST_LVL            GENMASK(20, 18)

​

#define PHY_R4                          0x10

    #define PHY_R4_PHY_CR_WRITE             BIT(0)

    #define PHY_R4_PHY_CR_READ              BIT(1)

    #define PHY_R4_PHY_CR_DATA_IN               GENMASK(17, 2)

    #define PHY_R4_PHY_CR_CAP_DATA              BIT(18)

    #define PHY_R4_PHY_CR_CAP_ADDR              BIT(19)

​

#define PHY_R5                          0x14

    #define PHY_R5_PHY_CR_DATA_OUT              GENMASK(15, 0)

    #define PHY_R5_PHY_CR_ACK               BIT(16)

    #define PHY_R5_PHY_BS_OUT               BIT(17)

​

struct phy_g12a_usb3_pcie_priv {

    struct regmap       *regmap;

#if CONFIG_IS_ENABLED(CLK)

    struct clk      clk;

#endif

    struct reset_ctl_bulk   resets;

};

​