uboot-phytec
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committed c8a8937b92fx
// SPDX-License-Identifier: GPL-2.0+/* * Copyright (C) 2018, STMicroelectronics - All Rights Reserved * Author: Fabrice Gasnier <fabrice.gasnier@st.com> * * Originally based on the Linux kernel v4.16 drivers/regulator/stm32-vrefbuf.c *//* STM32 VREFBUF registers *//* STM32 VREFBUF CSR bitfields */struct stm32_vrefbuf { void __iomem *base; struct clk clk; struct udevice *vdda_supply;};static const int stm32_vrefbuf_voltages[] = { /* Matches resp. VRS = 000b, 001b, 010b, 011b */ 2500000, 2048000, 1800000, 1500000,};static int stm32_vrefbuf_set_enable(struct udevice *dev, bool enable){ struct stm32_vrefbuf *priv = dev_get_priv(dev); u32 val; int ret; clrsetbits_le32(priv->base + STM32_VREFBUF_CSR, STM32_HIZ | STM32_ENVR, enable ? STM32_ENVR : STM32_HIZ); if (!enable) return 0; /* * Vrefbuf startup time depends on external capacitor: wait here for * VRR to be set. That means output has reached expected value. * ~650us sleep should be enough for caps up to 1.5uF. Use 10ms as * arbitrary timeout. */ ret = readl_poll_timeout(priv->base + STM32_VREFBUF_CSR, val, val & STM32_VRR, 10000); if (ret < 0) { dev_err(dev, "stm32 vrefbuf timed out: %d\n", ret); clrsetbits_le32(priv->base + STM32_VREFBUF_CSR, STM32_ENVR, STM32_HIZ); return ret; } return 0;}static int stm32_vrefbuf_get_enable(struct udevice *dev){ struct stm32_vrefbuf *priv = dev_get_priv(dev); return readl(priv->base + STM32_VREFBUF_CSR) & STM32_ENVR;}static int stm32_vrefbuf_set_value(struct udevice *dev, int uV){ struct stm32_vrefbuf *priv = dev_get_priv(dev); unsigned int i; for (i = 0; i < ARRAY_SIZE(stm32_vrefbuf_voltages); i++) { if (uV == stm32_vrefbuf_voltages[i]) { clrsetbits_le32(priv->base + STM32_VREFBUF_CSR, STM32_VRS, i << STM32_VRS_SHIFT); return 0; } } return -EINVAL;}static int stm32_vrefbuf_get_value(struct udevice *dev){ struct stm32_vrefbuf *priv = dev_get_priv(dev);