uboot-phytec

// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause

/*

 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved

 */

​

#include <common.h>

#include <clk.h>

#include <ram.h>

#include <reset.h>

#include <timer.h>

#include <asm/io.h>

#include <asm/arch/ddr.h>

#include <linux/iopoll.h>

#include "stm32mp1_ddr.h"

#include "stm32mp1_ddr_regs.h"

​

#define RCC_DDRITFCR        0xD8

​

#define RCC_DDRITFCR_DDRCAPBRST     (BIT(14))

#define RCC_DDRITFCR_DDRCAXIRST     (BIT(15))

#define RCC_DDRITFCR_DDRCORERST     (BIT(16))

#define RCC_DDRITFCR_DPHYAPBRST     (BIT(17))

#define RCC_DDRITFCR_DPHYRST        (BIT(18))

#define RCC_DDRITFCR_DPHYCTLRST     (BIT(19))

​

struct reg_desc {

    const char *name;

    u16 offset; /* offset for base address */

    u8 par_offset;  /* offset for parameter array */

};

​

#define INVALID_OFFSET  0xFF

​

#define DDRCTL_REG(x, y) \

    {#x,\

     offsetof(struct stm32mp1_ddrctl, x),\

     offsetof(struct y, x)}

​

#define DDRPHY_REG(x, y) \

    {#x,\

     offsetof(struct stm32mp1_ddrphy, x),\

     offsetof(struct y, x)}

​

#define DDRCTL_REG_REG(x)   DDRCTL_REG(x, stm32mp1_ddrctrl_reg)

static const struct reg_desc ddr_reg[] = {

    DDRCTL_REG_REG(mstr),

    DDRCTL_REG_REG(mrctrl0),

    DDRCTL_REG_REG(mrctrl1),

    DDRCTL_REG_REG(derateen),

    DDRCTL_REG_REG(derateint),

    DDRCTL_REG_REG(pwrctl),

    DDRCTL_REG_REG(pwrtmg),

    DDRCTL_REG_REG(hwlpctl),

    DDRCTL_REG_REG(rfshctl0),

    DDRCTL_REG_REG(rfshctl3),

    DDRCTL_REG_REG(crcparctl0),

    DDRCTL_REG_REG(zqctl0),

    DDRCTL_REG_REG(dfitmg0),

    DDRCTL_REG_REG(dfitmg1),

    DDRCTL_REG_REG(dfilpcfg0),

    DDRCTL_REG_REG(dfiupd0),

    DDRCTL_REG_REG(dfiupd1),

    DDRCTL_REG_REG(dfiupd2),

    DDRCTL_REG_REG(dfiphymstr),

    DDRCTL_REG_REG(odtmap),

    DDRCTL_REG_REG(dbg0),

    DDRCTL_REG_REG(dbg1),

    DDRCTL_REG_REG(dbgcmd),

    DDRCTL_REG_REG(poisoncfg),

    DDRCTL_REG_REG(pccfg),

};

​

#define DDRCTL_REG_TIMING(x)    DDRCTL_REG(x, stm32mp1_ddrctrl_timing)

static const struct reg_desc ddr_timing[] = {

    DDRCTL_REG_TIMING(rfshtmg),

    DDRCTL_REG_TIMING(dramtmg0),

    DDRCTL_REG_TIMING(dramtmg1),

    DDRCTL_REG_TIMING(dramtmg2),

    DDRCTL_REG_TIMING(dramtmg3),

    DDRCTL_REG_TIMING(dramtmg4),

    DDRCTL_REG_TIMING(dramtmg5),

    DDRCTL_REG_TIMING(dramtmg6),

    DDRCTL_REG_TIMING(dramtmg7),

    DDRCTL_REG_TIMING(dramtmg8),

    DDRCTL_REG_TIMING(dramtmg14),

    DDRCTL_REG_TIMING(odtcfg),

};

​

#define DDRCTL_REG_MAP(x)   DDRCTL_REG(x, stm32mp1_ddrctrl_map)

static const struct reg_desc ddr_map[] = {

    DDRCTL_REG_MAP(addrmap1),

    DDRCTL_REG_MAP(addrmap2),