uboot-phytec

/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */

/*

 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved

 */

​

#ifndef _RAM_STM32MP1_DDR_H

#define _RAM_STM32MP1_DDR_H

​

enum stm32mp1_ddr_interact_step {

    STEP_DDR_RESET,

    STEP_CTL_INIT,

    STEP_PHY_INIT,

    STEP_DDR_READY,

    STEP_RUN,

};

​

/* DDR CTL and DDR PHY REGISTERS */

struct stm32mp1_ddrctl;

struct stm32mp1_ddrphy;

​

/**

 * struct ddr_info

 *

 * @dev: pointer for the device

 * @info: UCLASS RAM information

 * @ctl: DDR controleur base address

 * @clk: DDR clock

 * @phy: DDR PHY base address

 * @rcc: rcc base address

 */

struct ddr_info {

    struct udevice *dev;

    struct ram_info info;

    struct clk clk;

    struct stm32mp1_ddrctl *ctl;

    struct stm32mp1_ddrphy *phy;

    u32 rcc;

};

​

struct stm32mp1_ddrctrl_reg {

    u32 mstr;

    u32 mrctrl0;

    u32 mrctrl1;

    u32 derateen;

    u32 derateint;

    u32 pwrctl;

    u32 pwrtmg;

    u32 hwlpctl;

    u32 rfshctl0;

    u32 rfshctl3;

    u32 crcparctl0;

    u32 zqctl0;

    u32 dfitmg0;

    u32 dfitmg1;

    u32 dfilpcfg0;

    u32 dfiupd0;

    u32 dfiupd1;

    u32 dfiupd2;

    u32 dfiphymstr;

    u32 odtmap;

    u32 dbg0;

    u32 dbg1;

    u32 dbgcmd;