uboot-phytec

/* SPDX-License-Identifier: GPL-2.0+ */

/*

 * SPI driver for rockchip

 *

 * (C) Copyright 2015 Google, Inc

 *

 * (C) Copyright 2008-2013 Rockchip Electronics

 * Peter, Software Engineering, <superpeter.cai@gmail.com>.

 */

​

#ifndef __RK_SPI_H

#define __RK_SPI_H

​

struct rockchip_spi {

    u32 ctrlr0;

    u32 ctrlr1;

    u32 enr;

    u32 ser;

    u32 baudr;

    u32 txftlr;

    u32 rxftlr;

    u32 txflr;

    u32 rxflr;

    u32 sr;

    u32 ipr;

    u32 imr;

    u32 isr;

    u32 risr;

    u32 icr;

    u32 dmacr;

    u32 dmatdlr;

    u32 dmardlr;        /* 0x44 */

    u32 reserved[0xef];

    u32 txdr[0x100];    /* 0x400 */

    u32 rxdr[0x100];    /* 0x800 */

};

​

/* CTRLR0 */

enum {

    DFS_SHIFT   = 0,    /* Data Frame Size */

    DFS_MASK    = 3,

    DFS_4BIT    = 0,

    DFS_8BIT,

    DFS_16BIT,

    DFS_RESV,

​

    CFS_SHIFT   = 2,    /* Control Frame Size */

    CFS_MASK    = 0xf,

​

    SCPH_SHIFT  = 6,    /* Serial Clock Phase */

    SCPH_MASK   = 1,

    SCPH_TOGMID = 0,    /* SCLK toggles in middle of first data bit */

    SCPH_TOGSTA,        /* SCLK toggles at start of first data bit */

​

    SCOL_SHIFT  = 7,    /* Serial Clock Polarity */

    SCOL_MASK   = 1,

    SCOL_LOW    = 0,    /* Inactive state of serial clock is low */

    SCOL_HIGH,      /* Inactive state of serial clock is high */

​

    CSM_SHIFT   = 8,    /* Chip Select Mode */

    CSM_MASK    = 0x3,

    CSM_KEEP    = 0,    /* ss_n stays low after each frame  */

    CSM_HALF,       /* ss_n high for half sclk_out cycles */