uboot-phytec

// SPDX-License-Identifier: GPL-2.0

/*

 * NVIDIA Tegra SPI controller (T114 and later)

 *

 * Copyright (c) 2010-2013 NVIDIA Corporation

 */

​

#include <common.h>

#include <dm.h>

#include <asm/io.h>

#include <asm/arch/clock.h>

#include <asm/arch-tegra/clk_rst.h>

#include <spi.h>

#include "tegra_spi.h"

​

/* COMMAND1 */

#define SPI_CMD1_GO         BIT(31)

#define SPI_CMD1_M_S            BIT(30)

#define SPI_CMD1_MODE_MASK      GENMASK(1, 0)

#define SPI_CMD1_MODE_SHIFT     28

#define SPI_CMD1_CS_SEL_MASK        GENMASK(1, 0)

#define SPI_CMD1_CS_SEL_SHIFT       26

#define SPI_CMD1_CS_POL_INACTIVE3   BIT(25)

#define SPI_CMD1_CS_POL_INACTIVE2   BIT(24)

#define SPI_CMD1_CS_POL_INACTIVE1   BIT(23)

#define SPI_CMD1_CS_POL_INACTIVE0   BIT(22)

#define SPI_CMD1_CS_SW_HW       BIT(21)

#define SPI_CMD1_CS_SW_VAL      BIT(20)

#define SPI_CMD1_IDLE_SDA_MASK      GENMASK(1, 0)

#define SPI_CMD1_IDLE_SDA_SHIFT     18

#define SPI_CMD1_BIDIR          BIT(17)

#define SPI_CMD1_LSBI_FE        BIT(16)

#define SPI_CMD1_LSBY_FE        BIT(15)

#define SPI_CMD1_BOTH_EN_BIT        BIT(14)

#define SPI_CMD1_BOTH_EN_BYTE       BIT(13)

#define SPI_CMD1_RX_EN          BIT(12)

#define SPI_CMD1_TX_EN          BIT(11)

#define SPI_CMD1_PACKED         BIT(5)

#define SPI_CMD1_BIT_LEN_MASK       GENMASK(4, 0)

#define SPI_CMD1_BIT_LEN_SHIFT      0

​

/* COMMAND2 */

#define SPI_CMD2_TX_CLK_TAP_DELAY   BIT(6)

#define SPI_CMD2_TX_CLK_TAP_DELAY_MASK  GENMASK(11, 6)

#define SPI_CMD2_RX_CLK_TAP_DELAY   BIT(0)

#define SPI_CMD2_RX_CLK_TAP_DELAY_MASK  GENMASK(5, 0)

​

/* TRANSFER STATUS */

#define SPI_XFER_STS_RDY        BIT(30)

​

/* FIFO STATUS */

#define SPI_FIFO_STS_CS_INACTIVE    BIT(31)

#define SPI_FIFO_STS_FRAME_END      BIT(30)

#define SPI_FIFO_STS_RX_FIFO_FLUSH  BIT(15)

#define SPI_FIFO_STS_TX_FIFO_FLUSH  BIT(14)

#define SPI_FIFO_STS_ERR        BIT(8)

#define SPI_FIFO_STS_TX_FIFO_OVF    BIT(7)

#define SPI_FIFO_STS_TX_FIFO_UNR    BIT(6)

#define SPI_FIFO_STS_RX_FIFO_OVF    BIT(5)

#define SPI_FIFO_STS_RX_FIFO_UNR    BIT(4)

#define SPI_FIFO_STS_TX_FIFO_FULL   BIT(3)

#define SPI_FIFO_STS_TX_FIFO_EMPTY  BIT(2)

#define SPI_FIFO_STS_RX_FIFO_FULL   BIT(1)

#define SPI_FIFO_STS_RX_FIFO_EMPTY  BIT(0)

​

#define SPI_TIMEOUT     1000

#define TEGRA_SPI_MAX_FREQ  52000000

​

struct spi_regs {

    u32 command1;   /* 000:SPI_COMMAND1 register */

    u32 command2;   /* 004:SPI_COMMAND2 register */

    u32 timing1;    /* 008:SPI_CS_TIM1 register */

    u32 timing2;    /* 00c:SPI_CS_TIM2 register */

    u32 xfer_status;/* 010:SPI_TRANS_STATUS register */

    u32 fifo_status;/* 014:SPI_FIFO_STATUS register */

    u32 tx_data;    /* 018:SPI_TX_DATA register */

    u32 rx_data;    /* 01c:SPI_RX_DATA register */

    u32 dma_ctl;    /* 020:SPI_DMA_CTL register */

    u32 dma_blk;    /* 024:SPI_DMA_BLK register */

    u32 rsvd[56];   /* 028-107 reserved */

    u32 tx_fifo;    /* 108:SPI_FIFO1 register */

    u32 rsvd2[31];  /* 10c-187 reserved */

    u32 rx_fifo;    /* 188:SPI_FIFO2 register */

    u32 spare_ctl;  /* 18c:SPI_SPARE_CTRL register */

};

​

struct tegra114_spi_priv {

    struct spi_regs *regs;

    unsigned int freq;

    unsigned int mode;

    int periph_id;

    int valid;