uboot-phytec

// SPDX-License-Identifier: GPL-2.0+

/*

 * (C) Copyright 2007

 * DENX Software Engineering, Anatolij Gustschin, agust@denx.de

 */

​

/*

 * mb862xx.c - Graphic interface for Fujitsu CoralP/Lime

 * PCI and video mode code was derived from smiLynxEM driver.

 */

​

#include <common.h>

​

#include <asm/io.h>

#include <env.h>

#include <pci.h>

#include <video_fb.h>

#include "videomodes.h"

#include <mb862xx.h>

​

#if defined(CONFIG_POST)

#include <post.h>

#endif

​

/*

 * Graphic Device

 */

GraphicDevice mb862xx;

​

/*

 * 32MB external RAM - 256K Chip MMIO = 0x1FC0000 ;

 */

#define VIDEO_MEM_SIZE  0x01FC0000

​

#if defined(CONFIG_PCI)

#if defined(CONFIG_VIDEO_CORALP)

​

static struct pci_device_id supported[] = {

    { PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_P },

    { PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_PA },

    { }

};

​

/* Internal clock frequency divider table, index is mode number */

unsigned int fr_div[] = { 0x00000f00, 0x00000900, 0x00000500 };

#endif

#endif

​

#if defined(CONFIG_VIDEO_CORALP)

#define rd_io       in32r

#define wr_io       out32r

#else

#define rd_io(addr) in_be32((volatile unsigned *)(addr))

#define wr_io(addr, val)    out_be32((volatile unsigned *)(addr), (val))

#endif

​

#define HOST_RD_REG(off)    rd_io((dev->frameAdrs + GC_HOST_BASE + (off)))

#define HOST_WR_REG(off, val)   wr_io((dev->frameAdrs + GC_HOST_BASE + (off)), \

                      (val))

#define DISP_RD_REG(off)    rd_io((dev->frameAdrs + GC_DISP_BASE + (off)))

#define DISP_WR_REG(off, val)   wr_io((dev->frameAdrs + GC_DISP_BASE + (off)), \

                      (val))

#define DE_RD_REG(off)      rd_io((dev->dprBase + (off)))