uboot-phytec

// SPDX-License-Identifier: GPL-2.0+

/*

 * Video driver for Marvell Armada XP SoC

 *

 * Initialization of LCD interface and setup of SPLASH screen image

 */

​

#include <common.h>

#include <video_fb.h>

#include <linux/mbus.h>

#include <asm/io.h>

#include <asm/arch/cpu.h>

#include <asm/arch/soc.h>

​

#define MVEBU_LCD_WIN_CONTROL(w)        (MVEBU_LCD_BASE + 0xf000 + ((w) << 4))

#define MVEBU_LCD_WIN_BASE(w)           (MVEBU_LCD_BASE + 0xf004 + ((w) << 4))

#define MVEBU_LCD_WIN_REMAP(w)          (MVEBU_LCD_BASE + 0xf00c + ((w) << 4))

​

#define MVEBU_LCD_CFG_DMA_START_ADDR_0  (MVEBU_LCD_BASE + 0x00cc)

#define MVEBU_LCD_CFG_DMA_START_ADDR_1  (MVEBU_LCD_BASE + 0x00dc)

​

#define MVEBU_LCD_CFG_GRA_START_ADDR0   (MVEBU_LCD_BASE + 0x00f4)

#define MVEBU_LCD_CFG_GRA_START_ADDR1   (MVEBU_LCD_BASE + 0x00f8)

#define MVEBU_LCD_CFG_GRA_PITCH     (MVEBU_LCD_BASE + 0x00fc)

#define MVEBU_LCD_SPU_GRA_OVSA_HPXL_VLN (MVEBU_LCD_BASE + 0x0100)

#define MVEBU_LCD_SPU_GRA_HPXL_VLN  (MVEBU_LCD_BASE + 0x0104)

#define MVEBU_LCD_SPU_GZM_HPXL_VLN  (MVEBU_LCD_BASE + 0x0108)

#define MVEBU_LCD_SPU_HWC_OVSA_HPXL_VLN (MVEBU_LCD_BASE + 0x010c)

#define MVEBU_LCD_SPU_HWC_HPXL_VLN  (MVEBU_LCD_BASE + 0x0110)

#define MVEBU_LCD_SPUT_V_H_TOTAL    (MVEBU_LCD_BASE + 0x0114)

#define MVEBU_LCD_SPU_V_H_ACTIVE    (MVEBU_LCD_BASE + 0x0118)

#define MVEBU_LCD_SPU_H_PORCH       (MVEBU_LCD_BASE + 0x011c)

#define MVEBU_LCD_SPU_V_PORCH       (MVEBU_LCD_BASE + 0x0120)

#define MVEBU_LCD_SPU_BLANKCOLOR    (MVEBU_LCD_BASE + 0x0124)

#define MVEBU_LCD_SPU_ALPHA_COLOR1  (MVEBU_LCD_BASE + 0x0128)

#define MVEBU_LCD_SPU_ALPHA_COLOR2  (MVEBU_LCD_BASE + 0x012c)

#define MVEBU_LCD_SPU_COLORKEY_Y    (MVEBU_LCD_BASE + 0x0130)

#define MVEBU_LCD_SPU_COLORKEY_U    (MVEBU_LCD_BASE + 0x0134)

#define MVEBU_LCD_SPU_COLORKEY_V    (MVEBU_LCD_BASE + 0x0138)

#define MVEBU_LCD_CFG_RDREG4F       (MVEBU_LCD_BASE + 0x013c)

#define MVEBU_LCD_SPU_SPI_RXDATA    (MVEBU_LCD_BASE + 0x0140)

#define MVEBU_LCD_SPU_ISA_RXDATA    (MVEBU_LCD_BASE + 0x0144)

#define MVEBU_LCD_SPU_DBG_ISA       (MVEBU_LCD_BASE + 0x0148)

​

#define MVEBU_LCD_SPU_HWC_RDDAT     (MVEBU_LCD_BASE + 0x0158)

#define MVEBU_LCD_SPU_GAMMA_RDDAT   (MVEBU_LCD_BASE + 0x015c)

#define MVEBU_LCD_SPU_PALETTE_RDDAT (MVEBU_LCD_BASE + 0x0160)

#define MVEBU_LCD_SPU_IOPAD_IN      (MVEBU_LCD_BASE + 0x0178)

#define MVEBU_LCD_FRAME_COUNT       (MVEBU_LCD_BASE + 0x017c)

#define MVEBU_LCD_SPU_DMA_CTRL0     (MVEBU_LCD_BASE + 0x0190)

#define MVEBU_LCD_SPU_DMA_CTRL1     (MVEBU_LCD_BASE + 0x0194)

#define MVEBU_LCD_SPU_SRAM_CTRL     (MVEBU_LCD_BASE + 0x0198)

#define MVEBU_LCD_SPU_SRAM_WRDAT    (MVEBU_LCD_BASE + 0x019c)

#define MVEBU_LCD_SPU_SRAM_PARA0    (MVEBU_LCD_BASE + 0x01a0)

#define MVEBU_LCD_SPU_SRAM_PARA1    (MVEBU_LCD_BASE + 0x01a4)

#define MVEBU_LCD_CFG_SCLK_DIV      (MVEBU_LCD_BASE + 0x01a8)

#define MVEBU_LCD_SPU_CONTRAST      (MVEBU_LCD_BASE + 0x01ac)

#define MVEBU_LCD_SPU_SATURATION    (MVEBU_LCD_BASE + 0x01b0)

#define MVEBU_LCD_SPU_CBSH_HUE      (MVEBU_LCD_BASE + 0x01b4)

#define MVEBU_LCD_SPU_DUMB_CTRL     (MVEBU_LCD_BASE + 0x01b8)

#define MVEBU_LCD_SPU_IOPAD_CONTROL (MVEBU_LCD_BASE + 0x01bc)

#define MVEBU_LCD_SPU_IRQ_ENA_2     (MVEBU_LCD_BASE + 0x01d8)

#define MVEBU_LCD_SPU_IRQ_ISR_2     (MVEBU_LCD_BASE + 0x01dc)

#define MVEBU_LCD_SPU_IRQ_ENA       (MVEBU_LCD_BASE + 0x01c0)

#define MVEBU_LCD_SPU_IRQ_ISR       (MVEBU_LCD_BASE + 0x01c4)

#define MVEBU_LCD_ADLL_CTRL     (MVEBU_LCD_BASE + 0x01c8)

#define MVEBU_LCD_CLK_DIS       (MVEBU_LCD_BASE + 0x01cc)

#define MVEBU_LCD_VGA_HVSYNC_DELAY  (MVEBU_LCD_BASE + 0x01d4)

#define MVEBU_LCD_CLK_CFG_0     (MVEBU_LCD_BASE + 0xf0a0)

#define MVEBU_LCD_CLK_CFG_1     (MVEBU_LCD_BASE + 0xf0a4)

#define MVEBU_LCD_LVDS_CLK_CFG      (MVEBU_LCD_BASE + 0xf0ac)

​

#define MVEBU_LVDS_PADS_REG     (MVEBU_SYSTEM_REG_BASE + 0xf0)

​

/* Setup Mbus Bridge Windows for LCD */

static void mvebu_lcd_conf_mbus_registers(void)

{

    const struct mbus_dram_target_info *dram;

    int i;

​

    dram = mvebu_mbus_dram_info();

​

    /* Disable windows, set size/base/remap to 0  */

    for (i = 0; i < 6; i++) {

        writel(0, MVEBU_LCD_WIN_CONTROL(i));

        writel(0, MVEBU_LCD_WIN_BASE(i));

        writel(0, MVEBU_LCD_WIN_REMAP(i));

    }

​

    /* Write LCD bridge window registers */

    for (i = 0; i < dram->num_cs; i++) {

        const struct mbus_dram_window *cs = dram->cs + i;