uboot-phytec

// SPDX-License-Identifier: GPL-2.0+

/*

 * Video driver for Marvell Armada XP SoC

 *

 * Initialization of LCD interface and setup of SPLASH screen image

 */

​

#include <common.h>

#include <dm.h>

#include <video.h>

#include <linux/mbus.h>

#include <asm/io.h>

#include <asm/arch/cpu.h>

#include <asm/arch/soc.h>

​

#define MVEBU_LCD_WIN_CONTROL(w)    (0xf000 + ((w) << 4))

#define MVEBU_LCD_WIN_BASE(w)       (0xf004 + ((w) << 4))

#define MVEBU_LCD_WIN_REMAP(w)      (0xf00c + ((w) << 4))

​

#define MVEBU_LCD_CFG_DMA_START_ADDR_0  0x00cc

#define MVEBU_LCD_CFG_DMA_START_ADDR_1  0x00dc

​

#define MVEBU_LCD_CFG_GRA_START_ADDR0   0x00f4

#define MVEBU_LCD_CFG_GRA_START_ADDR1   0x00f8

#define MVEBU_LCD_CFG_GRA_PITCH     0x00fc

#define MVEBU_LCD_SPU_GRA_OVSA_HPXL_VLN 0x0100

#define MVEBU_LCD_SPU_GRA_HPXL_VLN  0x0104

#define MVEBU_LCD_SPU_GZM_HPXL_VLN  0x0108

#define MVEBU_LCD_SPU_HWC_OVSA_HPXL_VLN 0x010c

#define MVEBU_LCD_SPU_HWC_HPXL_VLN  0x0110

#define MVEBU_LCD_SPUT_V_H_TOTAL    0x0114

#define MVEBU_LCD_SPU_V_H_ACTIVE    0x0118

#define MVEBU_LCD_SPU_H_PORCH       0x011c

#define MVEBU_LCD_SPU_V_PORCH       0x0120

#define MVEBU_LCD_SPU_BLANKCOLOR    0x0124

#define MVEBU_LCD_SPU_ALPHA_COLOR1  0x0128

#define MVEBU_LCD_SPU_ALPHA_COLOR2  0x012c

#define MVEBU_LCD_SPU_COLORKEY_Y    0x0130

#define MVEBU_LCD_SPU_COLORKEY_U    0x0134

#define MVEBU_LCD_SPU_COLORKEY_V    0x0138

#define MVEBU_LCD_CFG_RDREG4F       0x013c

#define MVEBU_LCD_SPU_SPI_RXDATA    0x0140

#define MVEBU_LCD_SPU_ISA_RXDATA    0x0144

#define MVEBU_LCD_SPU_DBG_ISA       0x0148

​

#define MVEBU_LCD_SPU_HWC_RDDAT     0x0158

#define MVEBU_LCD_SPU_GAMMA_RDDAT   0x015c

#define MVEBU_LCD_SPU_PALETTE_RDDAT 0x0160

#define MVEBU_LCD_SPU_IOPAD_IN      0x0178

#define MVEBU_LCD_FRAME_COUNT       0x017c

#define MVEBU_LCD_SPU_DMA_CTRL0     0x0190

#define MVEBU_LCD_SPU_DMA_CTRL1     0x0194

#define MVEBU_LCD_SPU_SRAM_CTRL     0x0198

#define MVEBU_LCD_SPU_SRAM_WRDAT    0x019c

#define MVEBU_LCD_SPU_SRAM_PARA0    0x01a0

#define MVEBU_LCD_SPU_SRAM_PARA1    0x01a4

#define MVEBU_LCD_CFG_SCLK_DIV      0x01a8

#define MVEBU_LCD_SPU_CONTRAST      0x01ac

#define MVEBU_LCD_SPU_SATURATION    0x01b0

#define MVEBU_LCD_SPU_CBSH_HUE      0x01b4

#define MVEBU_LCD_SPU_DUMB_CTRL     0x01b8

#define MVEBU_LCD_SPU_IOPAD_CONTROL 0x01bc

#define MVEBU_LCD_SPU_IRQ_ENA_2     0x01d8

#define MVEBU_LCD_SPU_IRQ_ISR_2     0x01dc

#define MVEBU_LCD_SPU_IRQ_ENA       0x01c0

#define MVEBU_LCD_SPU_IRQ_ISR       0x01c4

#define MVEBU_LCD_ADLL_CTRL     0x01c8

#define MVEBU_LCD_CLK_DIS       0x01cc

#define MVEBU_LCD_VGA_HVSYNC_DELAY  0x01d4

#define MVEBU_LCD_CLK_CFG_0     0xf0a0

#define MVEBU_LCD_CLK_CFG_1     0xf0a4

#define MVEBU_LCD_LVDS_CLK_CFG      0xf0ac

​

#define MVEBU_LVDS_PADS_REG     (MVEBU_SYSTEM_REG_BASE + 0xf0)

​

enum {

    /* Maximum LCD size we support */

    LCD_MAX_WIDTH       = 640,

    LCD_MAX_HEIGHT      = 480,

    LCD_MAX_LOG2_BPP    = VIDEO_BPP16,

};

​

struct mvebu_lcd_info {

    u32 fb_base;

    int x_res;

    int y_res;

    int x_fp;

    int y_fp;

    int x_bp;

    int y_bp;

};

​