uboot-phytec

// SPDX-License-Identifier: GPL-2.0+

/*

 * (C) 2015 Siarhei Siamashka <siarhei.siamashka@gmail.com>

 */

​

/*

 * Support for the SSD2828 bridge chip, which can take pixel data coming

 * from a parallel LCD interface and translate it on the flight into MIPI DSI

 * interface for driving a MIPI compatible TFT display.

 */

​

#include <common.h>

#include <mipi_display.h>

#include <asm/arch/gpio.h>

#include <asm/gpio.h>

​

#include "videomodes.h"

#include "ssd2828.h"

​

#define     SSD2828_DIR 0xB0

#define     SSD2828_VICR1   0xB1

#define     SSD2828_VICR2   0xB2

#define     SSD2828_VICR3   0xB3

#define     SSD2828_VICR4   0xB4

#define     SSD2828_VICR5   0xB5

#define     SSD2828_VICR6   0xB6

#define     SSD2828_CFGR    0xB7

#define     SSD2828_VCR 0xB8

#define     SSD2828_PCR 0xB9

#define     SSD2828_PLCR    0xBA

#define     SSD2828_CCR 0xBB

#define     SSD2828_PSCR1   0xBC

#define     SSD2828_PSCR2   0xBD

#define     SSD2828_PSCR3   0xBE

#define     SSD2828_PDR 0xBF

#define     SSD2828_OCR 0xC0

#define     SSD2828_MRSR    0xC1

#define     SSD2828_RDCR    0xC2

#define     SSD2828_ARSR    0xC3

#define     SSD2828_LCR 0xC4

#define     SSD2828_ICR 0xC5

#define     SSD2828_ISR 0xC6

#define     SSD2828_ESR 0xC7

#define     SSD2828_DAR1    0xC9

#define     SSD2828_DAR2    0xCA

#define     SSD2828_DAR3    0xCB

#define     SSD2828_DAR4    0xCC

#define     SSD2828_DAR5    0xCD

#define     SSD2828_DAR6    0xCE

#define     SSD2828_HTTR1   0xCF

#define     SSD2828_HTTR2   0xD0

#define     SSD2828_LRTR1   0xD1

#define     SSD2828_LRTR2   0xD2

#define     SSD2828_TSR 0xD3

#define     SSD2828_LRR 0xD4

#define     SSD2828_PLLR    0xD5

#define     SSD2828_TR  0xD6

#define     SSD2828_TECR    0xD7

#define     SSD2828_ACR1    0xD8

#define     SSD2828_ACR2    0xD9

#define     SSD2828_ACR3    0xDA

#define     SSD2828_ACR4    0xDB

#define     SSD2828_IOCR    0xDC

#define     SSD2828_VICR7   0xDD

#define     SSD2828_LCFR    0xDE

#define     SSD2828_DAR7    0xDF

#define     SSD2828_PUCR1   0xE0

#define     SSD2828_PUCR2   0xE1

#define     SSD2828_PUCR3   0xE2

#define     SSD2828_CBCR1   0xE9

#define     SSD2828_CBCR2   0xEA

#define     SSD2828_CBSR    0xEB

#define     SSD2828_ECR 0xEC

#define     SSD2828_VSDR    0xED

#define     SSD2828_TMR 0xEE

#define     SSD2828_GPIO1   0xEF

#define     SSD2828_GPIO2   0xF0

#define     SSD2828_DLYA01  0xF1

#define     SSD2828_DLYA23  0xF2

#define     SSD2828_DLYB01  0xF3

#define     SSD2828_DLYB23  0xF4

#define     SSD2828_DLYC01  0xF5

#define     SSD2828_DLYC23  0xF6

#define     SSD2828_ACR5    0xF7

#define     SSD2828_RR  0xFF

​

#define SSD2828_CFGR_HS                 (1 << 0)

#define SSD2828_CFGR_CKE                (1 << 1)

#define SSD2828_CFGR_SLP                (1 << 2)

#define SSD2828_CFGR_VEN                (1 << 3)

#define SSD2828_CFGR_HCLK               (1 << 4)

#define SSD2828_CFGR_CSS                (1 << 5)