uboot-phytec

// SPDX-License-Identifier: GPL-2.0+

/*

 * Marvell Armada 37xx SoC Watchdog Driver

 *

 * Marek Behun <marek.behun@nic.cz>

 */

​

#include <common.h>

#include <dm.h>

#include <wdt.h>

#include <asm/io.h>

#include <asm/arch/cpu.h>

#include <asm/arch/soc.h>

​

DECLARE_GLOBAL_DATA_PTR;

​

struct a37xx_wdt {

    void __iomem *sel_reg;

    void __iomem *reg;

    ulong clk_rate;

    u64 timeout;

};

​

/*

 * We use Counter 1 for watchdog timer, because so does Marvell's Linux by

 * default.

 */

​

#define CNTR_CTRL           0x10

#define CNTR_CTRL_ENABLE        0x0001

#define CNTR_CTRL_ACTIVE        0x0002

#define CNTR_CTRL_MODE_MASK     0x000c

#define CNTR_CTRL_MODE_ONESHOT      0x0000

#define CNTR_CTRL_PRESCALE_MASK     0xff00

#define CNTR_CTRL_PRESCALE_MIN      2

#define CNTR_CTRL_PRESCALE_SHIFT    8

​

#define CNTR_COUNT_LOW          0x14

#define CNTR_COUNT_HIGH         0x18

​

static void set_counter_value(struct a37xx_wdt *priv)

{

    writel(priv->timeout & 0xffffffff, priv->reg + CNTR_COUNT_LOW);

    writel(priv->timeout >> 32, priv->reg + CNTR_COUNT_HIGH);

}

​

static void a37xx_wdt_enable(struct a37xx_wdt *priv)

{

    u32 reg = readl(priv->reg + CNTR_CTRL);

​

    reg |= CNTR_CTRL_ENABLE;

    writel(reg, priv->reg + CNTR_CTRL);

}

​

static void a37xx_wdt_disable(struct a37xx_wdt *priv)

{

    u32 reg = readl(priv->reg + CNTR_CTRL);

​

    reg &= ~CNTR_CTRL_ENABLE;

    writel(reg, priv->reg + CNTR_CTRL);

}

​

static int a37xx_wdt_reset(struct udevice *dev)