Source of ti-pipe3-phy.c - uboot-phytec - PHYTEC BitBucket (Stash)

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        printf("%s: Invalid DPLL parameters\n", __func__);
        return -EINVAL;
    }
​
    val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION1);
    val &= ~PLL_REGN_MASK;
    val |= dpll_params->n << PLL_REGN_SHIFT;
    omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION1, val);
​
    val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION2);
    val &= ~PLL_SELFREQDCO_MASK;
    val &= ~(PLL_SELFREQDCO_MASK | PLL_IDLE);
    val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
    omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION2, val);
​
    val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION1);
    val &= ~PLL_REGM_MASK;
    val |= dpll_params->m << PLL_REGM_SHIFT;
    omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION1, val);
​
    val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION4);
    val &= ~PLL_REGM_F_MASK;
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        if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
            break;
    } while (--timeout);
​
    if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
        pr_err("%s: Failed to power down DPLL: PLL_STATUS 0x%x\n",
              __func__, val);
        return -EBUSY;
    }
​
    val = readl(pipe3->pll_reset_reg);
    writel(val | SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg);
    mdelay(1);
    writel(val & ~SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg);
    if (pipe3->pll_reset_reg) {
        val = readl(pipe3->pll_reset_reg);
        writel(val | SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg);
        mdelay(1);
        writel(val & ~SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg);
    }
​
    return 0;
}
​
static void *get_reg(struct udevice *dev, const char *name)
{
    struct udevice *syscon;
    struct regmap *regmap;
    const fdt32_t *cell;
    int len, err;
    void *base;
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    pipe3->pll_ctrl_base = map_physmem(addr, sz, MAP_NOCACHE);
    if (!pipe3->pll_ctrl_base) {
        pr_err("unable to remap pll ctrl\n");
        return -EINVAL;
    }
​
    pipe3->power_reg = get_reg(dev, "syscon-phy-power");
    if (!pipe3->power_reg)
        return -EINVAL;
​
    pipe3->pll_reset_reg = get_reg(dev, "syscon-pllreset");
    if (!pipe3->pll_reset_reg)
        return -EINVAL;
    if (device_is_compatible(dev, "ti,phy-pipe3-sata")) {
        pipe3->pll_reset_reg = get_reg(dev, "syscon-pllreset");
        if (!pipe3->pll_reset_reg)
            return -EINVAL;
    }
​
    pipe3->dpll_map = (struct pipe3_dpll_map *)dev_get_driver_data(dev);
​
    return 0;
}
​
static struct pipe3_dpll_map dpll_map_sata[] = {
    {12000000, {1000, 7, 4, 6, 0} },        /* 12 MHz */
    {16800000, {714, 7, 4, 6, 0} },         /* 16.8 MHz */
    {19200000, {625, 7, 4, 6, 0} },         /* 19.2 MHz */
    {20000000, {600, 7, 4, 6, 0} },         /* 20 MHz */
    {26000000, {461, 7, 4, 6, 0} },         /* 26 MHz */
    {38400000, {312, 7, 4, 6, 0} },         /* 38.4 MHz */
    { },                                    /* Terminator */
};
​
static struct pipe3_dpll_map dpll_map_usb[] = {
    {12000000, {1250, 5, 4, 20, 0} },   /* 12 MHz */
    {16800000, {3125, 20, 4, 20, 0} },  /* 16.8 MHz */
    {19200000, {1172, 8, 4, 20, 65537} },   /* 19.2 MHz */
    {20000000, {1000, 7, 4, 10, 0} },   /* 20 MHz */
    {26000000, {1250, 12, 4, 20, 0} },  /* 26 MHz */
    {38400000, {3125, 47, 4, 20, 92843} },  /* 38.4 MHz */
    { },                    /* Terminator */
};
​
static const struct udevice_id pipe3_phy_ids[] = {
    { .compatible = "ti,phy-pipe3-sata", .data = (ulong)&dpll_map_sata },
    { .compatible = "ti,omap-usb3", .data = (ulong)&dpll_map_usb},
    { }
};
​
static struct phy_ops pipe3_phy_ops = {
    .init = pipe3_init,
    .power_on = pipe3_power_on,
    .power_off = pipe3_power_off,
    .exit = pipe3_exit,
};
​