uboot-phytec
Public
Source
committed 2b69a67389f1
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// SPDX-License-Identifier: GPL-2.0+2
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/*3
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* Marvell Armada 37xx SoC Watchdog Driver4
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*5
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* Marek Behun <marek.behun@nic.cz>6
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*/7
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DECLARE_GLOBAL_DATA_PTR;16
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struct a37xx_wdt {18
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void __iomem *sel_reg;19
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void __iomem *reg;20
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ulong clk_rate;21
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u64 timeout;22
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};23
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24
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/*25
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* We use Counter 1 for watchdog timer, because so does Marvell's Linux by26
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* default.27
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*/28
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static void set_counter_value(struct a37xx_wdt *priv)42
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{43
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writel(priv->timeout & 0xffffffff, priv->reg + CNTR_COUNT_LOW);44
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writel(priv->timeout >> 32, priv->reg + CNTR_COUNT_HIGH);45
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}46
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static void a37xx_wdt_enable(struct a37xx_wdt *priv)48
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{49
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u32 reg = readl(priv->reg + CNTR_CTRL);50
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reg |= CNTR_CTRL_ENABLE;52
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writel(reg, priv->reg + CNTR_CTRL);53
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}54
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static void a37xx_wdt_disable(struct a37xx_wdt *priv)56
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{57
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u32 reg = readl(priv->reg + CNTR_CTRL);58
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reg &= ~CNTR_CTRL_ENABLE;60
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writel(reg, priv->reg + CNTR_CTRL);61
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}62
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static int a37xx_wdt_reset(struct udevice *dev)64
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{65
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struct a37xx_wdt *priv = dev_get_priv(dev);66
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if (!priv->timeout)68
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return -EINVAL;69
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a37xx_wdt_disable(priv);71
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set_counter_value(priv);72
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a37xx_wdt_enable(priv);73
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return 0;75
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}76
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static int a37xx_wdt_expire_now(struct udevice *dev, ulong flags)78
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{79
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struct a37xx_wdt *priv = dev_get_priv(dev);80
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a37xx_wdt_disable(priv);82
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priv->timeout = 0;83
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set_counter_value(priv);84
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a37xx_wdt_enable(priv);85
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return 0;87
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}88
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static int a37xx_wdt_start(struct udevice *dev, u64 ms, ulong flags)90
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{91
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struct a37xx_wdt *priv = dev_get_priv(dev);92
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u32 reg;93
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reg = readl(priv->reg + CNTR_CTRL);95
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if (reg & CNTR_CTRL_ACTIVE)97
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return -EBUSY;98
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/* set mode */100
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reg = (reg & ~CNTR_CTRL_MODE_MASK) | CNTR_CTRL_MODE_ONESHOT;101
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102
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/* set prescaler to the min value */103
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reg &= ~CNTR_CTRL_PRESCALE_MASK;104
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reg |= CNTR_CTRL_PRESCALE_MIN << CNTR_CTRL_PRESCALE_SHIFT;105
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priv->timeout = ms * priv->clk_rate / 1000 / CNTR_CTRL_PRESCALE_MIN;107
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writel(reg, priv->reg + CNTR_CTRL);109
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set_counter_value(priv);111
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a37xx_wdt_enable(priv);112
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return 0;114
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}115
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static int a37xx_wdt_stop(struct udevice *dev)117
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{118
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struct a37xx_wdt *priv = dev_get_priv(dev);119
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a37xx_wdt_disable(priv);121
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return 0;123
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}124
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static int a37xx_wdt_probe(struct udevice *dev)126
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{127
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struct a37xx_wdt *priv = dev_get_priv(dev);128
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fdt_addr_t addr;129
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addr = dev_read_addr_index(dev, 0);131
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if (addr == FDT_ADDR_T_NONE)132
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goto err;133
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priv->sel_reg = (void __iomem *)addr;134
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addr = dev_read_addr_index(dev, 1);136
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if (addr == FDT_ADDR_T_NONE)137
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goto err;138
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priv->reg = (void __iomem *)addr;139
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priv->clk_rate = (ulong)get_ref_clk() * 1000000;141
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a37xx_wdt_disable(priv);143
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/*145
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* We use timer 1 as watchdog timer (because Marvell's Linux uses that146
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* timer as default), therefore we only set bit TIMER1_IS_WCHDOG_TIMER.147
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*/148
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writel(1 << 1, priv->sel_reg);149
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return 0;151
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err:152
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dev_err(dev, "no io address\n");153
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return -ENODEV;154
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}155
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static const struct wdt_ops a37xx_wdt_ops = {157
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.start = a37xx_wdt_start,158
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.reset = a37xx_wdt_reset,159
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.stop = a37xx_wdt_stop,160
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.expire_now = a37xx_wdt_expire_now,161
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};162
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static const struct udevice_id a37xx_wdt_ids[] = {164
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{ .compatible = "marvell,armada-3700-wdt" },165
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{}166
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};167
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U_BOOT_DRIVER(a37xx_wdt) = {169
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.name = "armada_37xx_wdt",170
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.id = UCLASS_WDT,171
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.of_match = a37xx_wdt_ids,172
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.probe = a37xx_wdt_probe,173
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.priv_auto_alloc_size = sizeof(struct a37xx_wdt),174
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.ops = &a37xx_wdt_ops,175
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};