Commits
Imre Deak committed 1b85147b4b8
drm/i915/gen9_lp: Increase DDI PHY0 power well enabling timeout On GLK sporadic timeouts occur during PHY0 enabling. Based on logs it looks like they happen sometime after a system suspend/resume cycle, with the same power well enabling succeeding both before and after the failed one and no other problems observed. The current timeout in the code is not actually specified by BSpec, so let's try to increase that until a BSpec update. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105771 Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180409122716.4055-1-imre.deak@intel.com Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>