Commits
Jingchang Lu committed 1e2dbdefe72
dmaengine: fsl-edma: fixup reg offset and hw S/G support in big-endian model The offset of all 8-/16-bit registers in big-endian eDMA model are swapped in a 32-bit size opposite those in the little-endian model. The hardware Scatter/Gather requires the subsequent TCDs stored in memory in little endian independent of the register endian model, the eDMA engine will do the swap if need. This patch also use regular assignment for tcd variables r/w instead of with io function previously that may not always be true. Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>