Commits
Geert Uytterhoeven committed 246e232437e
clk: renesas: r8a77980: Correct parent clock of PCIEC0
According to the R-Car Gen3 Hardware Manual Errata for Rev 0.80 of
December 22, 2017, the parent clock of the PCIe module clock on R-Car
V3H is S2D2.
Fixes: ce15783c510a9905 ("clk: renesas: cpg-mssr: add R8A77980 support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>