Commits
Archit Taneja committed 26f7d1f4d9a
drm/msm/dsi: Parse DSI lanes via DT The DSI driver is currently unaware of how the DSI physical data lanes are mapped to the logical lanes provided by the DSI controller. Create a DT binding "qcom,data-lane-map" that provides this information on a given platform. The MSM DSI controller is restricted in terms of what all mappings it can support. The lane polarity is fixed for all the lanes, the clock lanes are fixed, and the data lanes can be swapped among each other only for a few combinations. Apply these restrictions when we parse the DT data. Cc: devicetree@vger.kernel.org Cc: Rob Herring <robh@kernel.org> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com> Acked-by: Rob Herring <robh@kernel.org>