Commits
Paul Cercueil committed 2b555a4b9ca
clk: ingenic: Add missing flag for UDC clock The UDC clock of the JZ4740 SoC can be gated, but the data structure representing it was missing the CGU_CLK_GATE flag to make it work. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>