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![Tudor Ambarus](https://secure.gravatar.com/avatar/1012715f9af6cd6a4d8d27ec852c455f.jpg?s=96&d=mm)
Tudor Ambarus committed 2e5c8888735
spi: atmel-quadspi: add support for sam9x60 qspi controller The sam9x60 qspi controller uses 2 clocks, one for the peripheral register access, the other for the qspi core and phy. Both are mandatory. It uses different transfer type bits in IFR register. It has dedicated registers to specify a read or a write instruction: Read Instruction Code Register (RICR) and Write Instruction Code Register (WICR). ICR/RICR/WICR have identical fields. Tested with sst26vf064b jedec,spi-nor flash. Backward compatibility test done on sama5d2 qspi controller and mx25l25635e jedec,spi-nor flash. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Mark Brown <broonie@kernel.org>