Commits
Abhishek Sahu committed 32cae024f71
clk: qcom: ipq8074: fix missing GPLL0 divider width GPLL0 uses 4 bits post divider which should be specified in clock driver structure. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>