Commits
Stephen Warren committed 44fefab459c
ARM: tegra: Fix Beaver's PCIe lane configuration Beaver's PCIe lane configuration most closely matches x2 x2 x2 rather than x4 x1 x1, since clocks 0 and 2 are used, and lanes 0 and 5 are used, and the only way those align is with a x2 x2 x2 configuration. Also, disable root port 1; there's nothing connected to it. Root port 0 is the on-board PCIe Ethernet, and port 2 is the mini-PCIe slot. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>