Commits
Chris Zhong committed 46dd2e28a90
ASoC: rockchip: correct the spdif clk The spdif mclk should be 128 times of sample rate, and there is a internal divider, the real rate of spdif mclk is mclk / (div + 1). Hence, the original driver always get the good frequency for 48000/96000/44100/192000. But for 32000, the mclk is incorrect, it should be 32000*128, but get 48000*128. Do not use the internal divider here, just set all mclk to 128 * sample rate directly. Signed-off-by: Chris Zhong <zyw@rock-chips.com> Signed-off-by: Mark Brown <broonie@kernel.org>