Commits
Merge tag 'meson-clk-4.21-1' of https://github.com/BayLibre/clk-meson into clk-meson Pull amlogic meson clk driver updates from Neil Armstrong: - Add GX video clocks - Switch to HHI syscon for meson8b - Fix meson8b cpu clock - Add support for meson8b CPU scaling - Add Meson8b CPU post-dividers clocks * tag 'meson-clk-4.21-1' of https://github.com/BayLibre/clk-meson: clk: meson: meson8b: add the CPU clock post divider clocks clk: meson: meson8b: rename cpu_div2/cpu_div3 to cpu_in_div2/cpu_in_div3 clk: meson: clk-regmap: add read-only gate ops clk: meson: meson8b: allow changing the CPU clock tree clk: meson: meson8b: run from the XTAL when changing the CPU frequency clk: meson: meson8b: add support for more M/N values in sys_pll clk: meson: meson8b: mark the CPU clock as CLK_IS_CRITICAL clk: meson: meson8b: do not use cpu_div3 for cpu_scale_out_sel clk: meson: clk-pll: check if the clock is already enabled clk: meson: meson8b: fix the width of the cpu_scale_div clock clk: meson: meson8b: fix incorrect divider mapping in cpu_scale_table clk: meson: meson8b: use the HHI syscon if available dt-bindings: clock: meson8b: use the registers from the HHI syscon clk: meson-gxbb: Add video clocks dt-bindings: clk: meson-gxbb: Add Video clock bindings clk: meson-gxbb: Fix HDMI PLL for GXL SoCs clk: meson: Add vid_pll divider driver dt-bindings: clock: meson8b: export the CPU post dividers
