Commits
Nicolas Ferre committed 581df9e1944
net/macb: fix ISR clear-on-write behavior only for some SoC Commit 749a2b6 (net/macb: clear tx/rx completion flags in ISR) introduces clear-on-write on ISR register. This behavior is not always implemented when using Cadence MACB/GEM and is breaking other platforms. We are using the Design Configuration Register 1 information and a capability property to actually activate this clear-on-write behavior on ISR. Reported-by: Hein Tibosch <hein_tibosch@yahoo.es> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Tested-by: Hein Tibosch <hein_tibosch@yahoo.es> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: David S. Miller <davem@davemloft.net>