Commits
Chen-Yu Tsai committed 7e81bda23ac
drm/sun4i: dotclock: Allow divider = 127 The dot clock divider is 7 bits wide, and the divider range is 1 ~ 127, or 6 ~ 127 if phase offsets are used. The 0 register value also represents a divider of 1 or bypass. Make the end condition of the for loop inclusive of 127 in the round_rate callback. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>