Commits
Anson Huang committed 7e99bce2f68
MLK-23131-2 soc: imx: busfreq-imx8mq: Correct dram pll clock for rate update When DRAM PLL clock is changed in TF-A, the DRAM PLL clock rate needs to be updated, previous implementation uses dram_pll_clk which is clock gate and it will NOT trigger clock rate update, need to use PLL type clock which has CLK_GET_RATE_NOCACHE flag set and will trigger clock rate recalculation. Otherwise, when system enters low bus mode, checking clock rate via "cat /sys/kernel/debug/clk/dram_core_clk/clk_rate" will NOT return the latest dram core clk rate. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Robin Gong <yibin.gong@nxp.com>