Commits
Jernej Skrabec committed a528872dbb8
clk: sunxi-ng: a83t: Add max. rate constraint to video PLLs It may happen that clock framework finds optimal video PLL rate above that which is really supported by HW. User manual doesn't really say what is upper limit for video PLLs on A83T. Because of that, use the maximum rate defined in BSP clk driver which is 3 GHz. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>