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Ville Syrjälä committed ad193bc6206
drm/i915: Enforce max hdisplay/hblank_start limits on HSW/BDW FDI The PCH transcoder registers are only 12 bits wide for the hdisplay and hblank_start values. On HSW/BDW the CPU side registers are 13 bits wide. intel_mode_valid() only checks against the higher limit (since we don't know where the mode is to be used), so an extra check is required against the FDI limits. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180615174406.12258-3-ville.syrjala@linux.intel.com Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>