Commits
Yoshihiro Shimoda committed b836005b4f9
watchdog: renesas_wdt: Add a few cycles delay According to the hardware manual of R-Car Gen2 and Gen3, software should wait a few RLCK cycles as following: - Delay 2 cycles before setting watchdog counter. - Delay 3 cycles before disabling module clock. So, this patch adds such delays. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>